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From: Usama on 27 Apr 2010 09:28
Hi,

I am implementing BMD design as explained in xapp1052(v2.5). Have
implemented the design on AvnetV5LXT/SXT PCIe Development Board using
the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE
10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using
to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using
only x1 lane of PCIe in my application. on both the machines i am
facing different problems.

Problem on S5000XVN
on this machine i have 2 x4 slots and 1 x16 slot. wen i
plug in a card on the one of the x4 slot my application runs perfectly
fine but when i plug it on the other x4 slot the data which i get is
not a valid data there is some garbage value shown in the data. What
could b the problem over here? Any idea ?

Problem on S3210SHLC
on this machine i am facing the problem that when i plug in
one of Avnet V5LXT/SXT PCIe Development Board the computer detects the
cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the
system is unable to detect it. i don't understand this strange
behavior why is it showing such a behavior. dose anyone know the
solution to this problem
From: d_s_klein on 27 Apr 2010 17:41
On Apr 27, 6:28 am, Usama <usama...(a)gmail.com> wrote:
> Hi,
>
> I am implementing BMD design as explained in xapp1052(v2.5). Have
> implemented the design on AvnetV5LXT/SXT PCIe Development Board using
> the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE
> 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using
> to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using
> only x1 lane of PCIe in my application. on both the machines i am
> facing different problems.
>
> Problem on S5000XVN
>             on this machine i have 2 x4 slots and 1 x16 slot. wen i
> plug in a card on the one of the x4 slot my application runs perfectly
> fine but when i plug it on the other x4 slot the data which i get is
> not a valid data there is some garbage value shown in the data. What
> could b the problem over here? Any idea ?
>
> Problem on S3210SHLC
>            on this machine i am facing the problem that when i plug in
> one of Avnet V5LXT/SXT PCIe Development Board the computer detects the
> cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the
> system is unable to detect it. i don't understand this strange
> behavior why is it showing such a behavior. dose anyone know the
> solution to this problem

The PCIe link is not working, (probably) because the lane aggregation
isn't happening properly.

Until you know enough about PCIe, and especially how lanes become
links, no one will be able to help you.

RK
From: Usama on 28 Apr 2010 02:24
On Apr 28, 2:41 am, d_s_klein <d_s_kl...(a)yahoo.com> wrote:
> On Apr 27, 6:28 am, Usama <usama...(a)gmail.com> wrote:
>
>
>
>
>
> > Hi,
>
> > I am implementing BMD design as explained in xapp1052(v2.5). Have
> > implemented the design on AvnetV5LXT/SXT PCIe Development Board using
> > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE
> > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using
> > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using
> > only x1 lane of PCIe in my application. on both the machines i am
> > facing different problems.
>
> > Problem on S5000XVN
> >             on this machine i have 2 x4 slots and 1 x16 slot. wen i
> > plug in a card on the one of the x4 slot my application runs perfectly
> > fine but when i plug it on the other x4 slot the data which i get is
> > not a valid data there is some garbage value shown in the data. What
> > could b the problem over here? Any idea ?
>
> > Problem on S3210SHLC
> >            on this machine i am facing the problem that when i plug in
> > one of Avnet V5LXT/SXT PCIe Development Board the computer detects the
> > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the
> > system is unable to detect it. i don't understand this strange
> > behavior why is it showing such a behavior. dose anyone know the
> > solution to this problem
>
> The PCIe link is not working, (probably) because the lane aggregation
> isn't happening properly.
>
> Until you know enough about PCIe, and especially how lanes become
> links, no one will be able to help you.
>
> RK

Thanks for the reply RK,
I guess I was not very clear in the problem description. Let me try to
put more details and may be it will help others out to help me solve
this problem.
I have three motherboards.
1. D945GCCR (reference motherboard)
2. S5000XVN
3. S3210SHLC


Th FPGA board that I have supports x8 mechanical connector. The Xilinx
BMD design that I have implemented just uses single lane so actually
it is configured to operate in x1 mode.

The S5000XVN motherboard has three PCIe slots. Two are with x8
mechanical slots supporting x4 mode and the one is with x16 mechanical
slot supporting upto x16 mode.
================================
Total Mechanical Mode
================================
2 x8 x4
1 x16 x16

The x16 slot houses NVidia VGA card on the motherboard. So we are left
with the remaining two slots. Theoretically, my BMD design should work
on all these slots as it is supported both mechanically and mode wise
as well (only implemented x1 mode on the FPGA board). However, the
problems that I have mentioned remain the same. On this particular
motherboard, I get garbage data mixed with actual data. So I am able
to get expected data but there are few locations read out as garbage
values. Interestingly, when I use the same FPGA board on reference
machine with intel motherboard (D945GCCR) with x16 mechanical
connector supporting upto x16 mode, the same FPGA board behaves as
expected with NO garbage values.

Now lets have a look at the second mother board which is S3210SHLC.
This particular motherboard has the following PCIe slots with
mechanical slots and lane modes supported.

================================
Total Mechanical Mode
================================
1 x8 x4
1 x8 x8
1 x16 x8

On this particular motherboard, the behavior is totally different. I
have four identical Avnet FPGA boards, all loaded with the same
bitstreams. All these boards are successfully detected on S5000XVN
motherboard and on a reference motherboard but the strange thing about
the subject motherboard (S3210SHLC) is, there is only one FPGA board
out of those four FPGA boards which gets detected on this motherboard,
the rest of the FPGA boards are not detected on OS bootup. The other
problem which is common in this motherboard and the previous
motherboard is, when the same FPGA board is plugged into the x8
mechanical slot supporting x4 lanes, I get garbage values coming out
of the FPGA along with actual data. But when plugged in x8 and x16
mechanical slots supporting x8 modes on both the slots, the data is
read out perfectly.

I have been able to establish one common thing in all these tests. All
those PCIe slots which mechanically support x8 PCIe cards but
downgraded to support upto x4 lanes create problems. All those slots
which mechanically support x8 connector FPGA card and support x8 lane
mode works fine. The other FPGAs not getting detected and only one
getting detected is still confusing.

I hope I am very clear this time in adding details and I am hopeful to
get more help on this.

Thanks
UBA




From: maverick on 28 Apr 2010 02:48
On Apr 28, 11:24 am, Usama <usama...(a)gmail.com> wrote:
> On Apr 28, 2:41 am, d_s_klein <d_s_kl...(a)yahoo.com> wrote:
>
>
>
>
>
> > On Apr 27, 6:28 am, Usama <usama...(a)gmail.com> wrote:
>
> > > Hi,
>
> > > I am implementing BMD design as explained in xapp1052(v2.5). Have
> > > implemented the design on AvnetV5LXT/SXT PCIe Development Board using
> > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE
> > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using
> > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using
> > > only x1 lane of PCIe in my application. on both the machines i am
> > > facing different problems.
>
> > > Problem on S5000XVN
> > >             on this machine i have 2 x4 slots and 1 x16 slot. wen i
> > > plug in a card on the one of the x4 slot my application runs perfectly
> > > fine but when i plug it on the other x4 slot the data which i get is
> > > not a valid data there is some garbage value shown in the data. What
> > > could b the problem over here? Any idea ?
>
> > > Problem on S3210SHLC
> > >            on this machine i am facing the problem that when i plug in
> > > one of Avnet V5LXT/SXT PCIe Development Board the computer detects the
> > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the
> > > system is unable to detect it. i don't understand this strange
> > > behavior why is it showing such a behavior. dose anyone know the
> > > solution to this problem
>
> > The PCIe link is not working, (probably) because the lane aggregation
> > isn't happening properly.
>
> > Until you know enough about PCIe, and especially how lanes become
> > links, no one will be able to help you.
>
> > RK
>
> Thanks for the reply RK,
> I guess I was not very clear in the problem description. Let me try to
> put more details and may be it will help others out to help me solve
> this problem.
>  I have three motherboards.
> 1. D945GCCR   (reference motherboard)
> 2. S5000XVN
> 3. S3210SHLC
>
> Th FPGA board that I have supports x8 mechanical connector. The Xilinx
> BMD design that I have implemented just uses single lane so actually
> it is configured to operate in x1 mode.
>
> The S5000XVN motherboard has three PCIe slots. Two are with x8
> mechanical slots supporting x4 mode and the one is with x16 mechanical
> slot supporting upto x16 mode.
> ================================
> Total           Mechanical              Mode
> ================================
> 2                   x8                           x4
> 1                   x16                        x16
>
> The x16 slot houses NVidia VGA card on the motherboard. So we are left
> with the remaining two slots. Theoretically, my BMD design should work
> on all these slots as it is supported both mechanically and mode wise
> as well (only implemented x1 mode on the FPGA board). However, the
> problems that I have mentioned remain the same. On this particular
> motherboard, I get garbage data mixed with actual data. So I am able
> to get expected data but there are few locations read out as garbage
> values. Interestingly, when I use the same FPGA board on reference
> machine with intel motherboard (D945GCCR) with x16 mechanical
> connector supporting upto x16 mode, the same FPGA board behaves as
> expected with NO garbage values.
>
> Now lets have a look at the second mother board which is S3210SHLC.
> This particular motherboard has the following PCIe slots with
> mechanical slots and lane modes supported.
>
> ================================
> Total           Mechanical              Mode
> ================================
> 1                   x8                           x4
> 1                   x8                           x8
> 1                   x16                         x8
>
> On this particular motherboard, the behavior is totally different. I
> have four identical Avnet FPGA boards, all loaded with the same
> bitstreams. All these boards are successfully detected on S5000XVN
> motherboard and on a reference motherboard but the strange thing about
> the subject motherboard (S3210SHLC) is, there is only one FPGA board
> out of those four FPGA boards which gets detected on this motherboard,
> the rest of the FPGA boards are not detected on OS bootup. The other
> problem which is common in this motherboard and the previous
> motherboard is, when the same FPGA board is plugged into the x8
> mechanical slot supporting x4 lanes, I get garbage values coming out
> of the FPGA along with actual data. But when plugged in x8 and x16
> mechanical slots supporting x8 modes on both the slots, the data is
> read out perfectly.
>
> I have been able to establish one common thing in all these tests. All
> those PCIe slots which mechanically support x8 PCIe cards but
> downgraded to support upto x4 lanes create problems. All those slots
> which mechanically support x8 connector FPGA card and support x8 lane
> mode works fine. The other FPGAs not getting detected and only one
> getting detected is still confusing.
>
> I hope I am very clear this time in adding details and I am hopeful to
> get more help on this.
>
> Thanks
> UBA- Hide quoted text -
>
> - Show quoted text -

So if I summarize your motherboard problem having spitting garbage
values and map it on the same table you provided, is this how it will
look like?

S5000XVN motherboard
=========================================
Total Mechanical Mode Test Rsults
========================================
2 x8 x4
FAIL(garbage values)
1 x16 x16 couldnot
test, slot not available



S3210SHLC motherboard
=======================================
Total Mechanical Mode Test Rsults

======================================
1 x8 x4
FAIL(garbage values)
1 x8 x8 PASS
1 x16 x8 PASS


D945GCCR (reference motherboard)
=======================================
Total Mechanical Mode Test Rsults

======================================
1 x16 x16 PASS


maverick

From: Usama on 28 Apr 2010 02:55
On Apr 28, 11:48 am, maverick <sheikh.m.far...(a)gmail.com> wrote:
> On Apr 28, 11:24 am, Usama <usama...(a)gmail.com> wrote:
>
>
>
>
>
> > On Apr 28, 2:41 am, d_s_klein <d_s_kl...(a)yahoo.com> wrote:
>
> > > On Apr 27, 6:28 am, Usama <usama...(a)gmail.com> wrote:
>
> > > > Hi,
>
> > > > I am implementing BMD design as explained in xapp1052(v2.5). Have
> > > > implemented the design on AvnetV5LXT/SXT PCIe Development Board using
> > > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE
> > > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using
> > > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using
> > > > only x1 lane of PCIe in my application. on both the machines i am
> > > > facing different problems.
>
> > > > Problem on S5000XVN
> > > >             on this machine i have 2 x4 slots and 1 x16 slot. wen i
> > > > plug in a card on the one of the x4 slot my application runs perfectly
> > > > fine but when i plug it on the other x4 slot the data which i get is
> > > > not a valid data there is some garbage value shown in the data. What
> > > > could b the problem over here? Any idea ?
>
> > > > Problem on S3210SHLC
> > > >            on this machine i am facing the problem that when i plug in
> > > > one of Avnet V5LXT/SXT PCIe Development Board the computer detects the
> > > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the
> > > > system is unable to detect it. i don't understand this strange
> > > > behavior why is it showing such a behavior. dose anyone know the
> > > > solution to this problem
>
> > > The PCIe link is not working, (probably) because the lane aggregation
> > > isn't happening properly.
>
> > > Until you know enough about PCIe, and especially how lanes become
> > > links, no one will be able to help you.
>
> > > RK
>
> > Thanks for the reply RK,
> > I guess I was not very clear in the problem description. Let me try to
> > put more details and may be it will help others out to help me solve
> > this problem.
> >  I have three motherboards.
> > 1. D945GCCR   (reference motherboard)
> > 2. S5000XVN
> > 3. S3210SHLC
>
> > Th FPGA board that I have supports x8 mechanical connector. The Xilinx
> > BMD design that I have implemented just uses single lane so actually
> > it is configured to operate in x1 mode.
>
> > The S5000XVN motherboard has three PCIe slots. Two are with x8
> > mechanical slots supporting x4 mode and the one is with x16 mechanical
> > slot supporting upto x16 mode.
> > ================================
> > Total           Mechanical              Mode
> > ================================
> > 2                   x8                           x4
> > 1                   x16                        x16
>
> > The x16 slot houses NVidia VGA card on the motherboard. So we are left
> > with the remaining two slots. Theoretically, my BMD design should work
> > on all these slots as it is supported both mechanically and mode wise
> > as well (only implemented x1 mode on the FPGA board). However, the
> > problems that I have mentioned remain the same. On this particular
> > motherboard, I get garbage data mixed with actual data. So I am able
> > to get expected data but there are few locations read out as garbage
> > values. Interestingly, when I use the same FPGA board on reference
> > machine with intel motherboard (D945GCCR) with x16 mechanical
> > connector supporting upto x16 mode, the same FPGA board behaves as
> > expected with NO garbage values.
>
> > Now lets have a look at the second mother board which is S3210SHLC.
> > This particular motherboard has the following PCIe slots with
> > mechanical slots and lane modes supported.
>
> > ================================
> > Total           Mechanical              Mode
> > ================================
> > 1                   x8                           x4
> > 1                   x8                           x8
> > 1                   x16                         x8
>
> > On this particular motherboard, the behavior is totally different. I
> > have four identical Avnet FPGA boards, all loaded with the same
> > bitstreams. All these boards are successfully detected on S5000XVN
> > motherboard and on a reference motherboard but the strange thing about
> > the subject motherboard (S3210SHLC) is, there is only one FPGA board
> > out of those four FPGA boards which gets detected on this motherboard,
> > the rest of the FPGA boards are not detected on OS bootup. The other
> > problem which is common in this motherboard and the previous
> > motherboard is, when the same FPGA board is plugged into the x8
> > mechanical slot supporting x4 lanes, I get garbage values coming out
> > of the FPGA along with actual data. But when plugged in x8 and x16
> > mechanical slots supporting x8 modes on both the slots, the data is
> > read out perfectly.
>
> > I have been able to establish one common thing in all these tests. All
> > those PCIe slots which mechanically support x8 PCIe cards but
> > downgraded to support upto x4 lanes create problems. All those slots
> > which mechanically support x8 connector FPGA card and support x8 lane
> > mode works fine. The other FPGAs not getting detected and only one
> > getting detected is still confusing.
>
> > I hope I am very clear this time in adding details and I am hopeful to
> > get more help on this.
>
> > Thanks
> > UBA- Hide quoted text -
>
> > - Show quoted text -
>
> So if I summarize your motherboard problem having spitting garbage
> values and map it on the same table you provided, is this how it will
> look like?
>
> S5000XVN motherboard
> =========================================
>  Total        Mechanical    Mode       Test Rsults
>  ========================================
>  2               x8           x4 FAIL(garbage values)
>  1               x16           x16    slot not available
>
> S3210SHLC motherboard
> =======================================
>  Total       Mechanical      Mode      Test Rsults
>
>  ======================================
 1                x8              x4 FAIL(garbage values)
>  1               x8         x8       PASS
>  1               x16        x8       PASS
>
> D945GCCR   (reference motherboard)
> =======================================
>  Total           Mechanical          Mode        Test Rsults
>
>  ======================================
>  1                   x16                      x16           PASS
>
> maverick

Thats absolutely right.

The other problem is the unsuccessful detection of few Avnet FPGA
boards.
UBA
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