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From: karthikbalaguru on 17 Mar 2010 21:38
On Mar 17, 10:07 pm, Eric Jacobsen <eric.jacob...(a)ieee.org> wrote:
> On 3/16/2010 4:23 PM, onkars wrote:
>
> > Can anyone talk on the state of the art FFT implementations in hardware ---
> > ASIC, IP cores etc. -- in terms of throughput?
> > We are looking for something in excess of 5G.
>
> > Thanks.
>
> A lot of the relevant FFT hardware architecture research was done
> decades ago when hardware resources were much more expensive than they
> are now.  There are still a lot of tradeoffs depending on what you
> really want, the length of the vector or whether it needs to support
> multiple vector lengths, etc., etc.
>
> I'd look around for books and articles from the 80s or maybe even early
> 90s.   The number of architectures just to do FFTs is surprising.
>
> If you really just want throughput as the main design criterion, as
> cheap as gates and memory are these days I'd think it'd be worth looking
> at just doing a straightforward implementation where each stage runs all
> of the butterflies in parallel and all of the stages are pipelined.   In
> other words, each stage has its own hardware, each butterfly in each
> stage has its own hardware.

Interesting approach, but how about the cost factor ?

> You may not need to get fancy at all.   It'd
> be much bigger than a more hardware or power efficient implementation,
> but it'd sustain high throughput.
>

Karthik Balaguru
From: Jerry Avins on 17 Mar 2010 21:53
karthikbalaguru wrote:

...

> Interesting approach, but how about the cost factor ?

You didn't list cost as a criterion. Small. Cheap. Fast. Pick any two.

...

Jerry
--
Discovery consists of seeing what everybody has seen, and thinking what
nobody has thought. .. Albert Szent-Gyorgi
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From: Steve Pope on 17 Mar 2010 22:12
karthikbalaguru <karthikbalaguru79(a)gmail.com> wrote:

>On Mar 17, 10:07�pm, Eric Jacobsen <eric.jacob...(a)ieee.org> wrote:
>> If you really just want throughput as the main design criterion, as
>> cheap as gates and memory are these days I'd think it'd be worth looking
>> at just doing a straightforward implementation where each stage runs all
>> of the butterflies in parallel and all of the stages are pipelined. � In
>> other words, each stage has its own hardware, each butterfly in each
>> stage has its own hardware.

>Interesting approach, but how about the cost factor ?

So long as the multiplier utilization is close to 100%,
and so long as your attained throughput is not overkill
relative to your spec, you have not overdesigned and
you have probably created an efficient design.

60 band GHz OFDM implementors need to implement an FFT design
with specs similar to the OP's. It has not held them back from
doing so.

Steve
From: cfelton on 18 Mar 2010 08:33

>> ASIC, IP cores etc. -- in terms of throughput?
>> We are looking for something in excess of 5G.
>>

Dillon Engineering (http://www.dilloneng.com/fft_ip) advertises 25 GSPS
(potential) in Virtex5. Also, ASIC quality IP depending on technology and
clock speeds should be able to better in an ASIC.

From: Lemon Tree on 20 Mar 2010 23:19
You can take a look at nVidia CUDA systems:
http://www.nvidia.co.uk/object/cuda_home_new_uk.html
Basically 1000 Billion flops per second, enough? Or do you need
several cards.
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