Highest throughput FFT implementation in hardware
in [DSP]
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From: onkars on 16 Mar 2010 19:23 Can anyone talk on the state of the art FFT implementations in hardware --- ASIC, IP cores etc. -- in terms of throughput? We are looking for something in excess of 5G. Thanks.
From: Richard Owlett on 17 Mar 2010 02:52 onkars wrote: > Can anyone talk on the state of the art FFT implementations in hardware --- > ASIC, IP cores etc. -- in terms of throughput? > We are looking for something in excess of 5G. > > Thanks. > > unobit OR GIGAB precision *LOL*
From: Darol Klawetter on 17 Mar 2010 10:35 On Mar 16, 6:21 pm, "onkars" <onkar.sarode(a)n_o_s_p_a_m.gmail.com> wrote: > Can anyone talk on the state of the art FFT implementations in hardware --- > ASIC, IP cores etc. -- in terms of throughput? > We are looking for something in excess of 5G. > > Thanks. See Dillon Engineering for FFT IP http://www.dilloneng.com/fft_ip Darol Klawetter
From: onkars on 17 Mar 2010 11:58 >On Mar 16, 6:21=A0pm, "onkars" <onkar.sarode(a)n_o_s_p_a_m.gmail.com> >wrote: >> Can anyone talk on the state of the art FFT implementations in hardware -= >-- >> ASIC, IP cores etc. -- in terms of throughput? >> We are looking for something in excess of 5G. >> >> Thanks. > >See Dillon Engineering for FFT IP > >http://www.dilloneng.com/fft_ip > >Darol Klawetter > Thanks Darol
From: Eric Jacobsen on 17 Mar 2010 13:07
On 3/16/2010 4:23 PM, onkars wrote: > Can anyone talk on the state of the art FFT implementations in hardware --- > ASIC, IP cores etc. -- in terms of throughput? > We are looking for something in excess of 5G. > > Thanks. A lot of the relevant FFT hardware architecture research was done decades ago when hardware resources were much more expensive than they are now. There are still a lot of tradeoffs depending on what you really want, the length of the vector or whether it needs to support multiple vector lengths, etc., etc. I'd look around for books and articles from the 80s or maybe even early 90s. The number of architectures just to do FFTs is surprising. If you really just want throughput as the main design criterion, as cheap as gates and memory are these days I'd think it'd be worth looking at just doing a straightforward implementation where each stage runs all of the butterflies in parallel and all of the stages are pipelined. In other words, each stage has its own hardware, each butterfly in each stage has its own hardware. You may not need to get fancy at all. It'd be much bigger than a more hardware or power efficient implementation, but it'd sustain high throughput. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com |