How Many Processor Cores Are Enough?
|
From: Eugene Miya on 3 Oct 2006 19:41 In article <45228599$1(a)darkstar>, eugene(a)cse.ucsc.edu (Eugene Miya) writes: >|> You have to remember to keep the important keyword, PIM, in case >|> threading gets cut. In article <efu0uf$omt$1(a)gemini.csx.cam.ac.uk>, Nick Maclaren <nmm1(a)cus.cam.ac.uk> wrote: >It will be amusing to see what meaning that term attaches itself to, >assuming that some such technologies arrive in the general market. You mean like Personal Information Management (a CACM special issue), and other lossy forms of acronym creation? But outside the perview of architecture (computer). >|> When? Well. That's hard to say. It may be never the rate the Crusade >|> is going. > >What Crusade? I know of only one current one and it is OT. Let's >not bring it up again. Your albatross Nick. >|> Certainly people in the field have seen them. One of the >|> former posters most pissed at Nick likely saw them. The first were >|> integrated into preexisting boxes of manufacturers you have already >|> heard of as well as lesser known more expensive packages. >|> But the scale and degree and current numbers I have no idea now. >|> Museums only get access to things in some cases ages, decades after >|> they are done. They supposedily just look any other rectangular box. > >Until and unless someone is prepared to describe what he saw, it is >hard to tell whether what they saw WAS just a random, off-the-shelf >computer box containing a lot of hot air. After all, could the >person who told THEM "this box is full of PIMs" be telling porkies? >Nah. Nobody EVER does that. You can say the Emperor has no clothes. You aren't an American tax payer. What's needed are measured comparisons. >More seriously, those of us with Half a Clue (as well as the people who >are inside the business) have been saying for two decades that there has >never been any difficulty for the major companies to make such things; >the problem is and always has been to turn them into something that >can be used effectively by mere mortals for typical tasks. Well unclasified TRs exist on the programming languages. And equivalents which aren't PIMs exist like... http://en.wikipedia.org/wiki/Deep_Crack %Q Electronic Frontier Foundation %A John Gilmore %T Cracking DES: Secrets of Encryption Research, Wiretap Politics & Chip Design %I Electronic Frontier Foundation %C San Francisco %D May 1998 %K book, text, Deep Crack, old Data Encryption Standard, %O ISBN: 1565925203 But that's not a PIM either. >And it is the latter aspect that is interesting, not whether there are >a few specialised systems built to amuse the spooks. I recall that the same was just send about computers from the 40s to the 60s. --
From: Ron Nicholson on 3 Oct 2006 20:26 Felger Carbon wrote: > A very few power users - say, 3 to 5 in the world - will be able to use lots > and lots of cores. The vast majority of the public will not run more than > one task at a time, which at this time means only one core. The vast majority of the public buys shrinkwrap software which has managed to run more slowly even when given on the order of 1000 times more memory and 1000 times more CPU power over the past few years. These users will still complain about slowness in animating the GUI when the real-time raytracing done using nearly 1 CPU per pixel doesn't keep up as they shake the breakfast crumbs off of their wearable display. And/or etc. IMHO. YMMV. -- rhn A.T nicholson d.0.t C-o-M
From: ranjit_mathews@yahoo.com on 3 Oct 2006 21:47 Terje Mathisen wrote: > jsavard(a)ecn.ab.ca wrote: > > This is where the microcomputer revolution has ended up at present - > > where it's almost impossible to design a "supercomputer" that has > > better single-thread performance than your desktop PC. Not totally > > impossible, though; there is room to get ahead of that curve a little > > bit - the Itanium is proof of that, for example. > > Except that the Itanium doesn't really outperform 'standard' PC cpus on > SpecInt, only on FP stuff, and barely there as well. How does the Itanium compare in terms of SpecInts PER GHz?
From: Bernd Paysan on 3 Oct 2006 08:50 already5chosen(a)yahoo.com wrote: > > Del Cecchi wrote: >> >> Well, if you count work applications there are many. SPICE. DRC/LVS, >> extraction, simulation....... >> >> That's why server farms were invented. >> >> del >> > > How many of those are both > 1. Efficiently parallelizable > 2. But not embarrassingly parallel > Because for embarrassingly-parallel case multicore is no better than > SMP, except for the price and both multicore and SMP often no better > than distributed computation (clusters, MPP). Ok, DRC and extraction falls into the embarrasingly parallel cathegory (since you can divide the chip into small rectangles, and do the DRC/extract there). SPICE itself is a sequential algorithm, and completely ignores the speed of light, but in fact, the thing you want to simulate is actually embarassingly parallel (so you could write a simulator that is embarassingly parallel). Verilog simulation is in principle embarassingly parallel, as well; the way the simulation works (event-driven simulation) allows to actually build parallel simulators. FPGA synthesis? Could be parallelized as well. The sad fact is that almost nobody does this. There are parallelized synthesis tools, and even more important, parallelized place&route tools. -- Bernd Paysan "If you want it done right, you have to do it yourself" http://www.jwdt.com/~paysan/
From: Dennis M. O'Connor on 4 Oct 2006 00:20
<ranjit_mathews(a)yahoo.com> wrote .. > Terje Mathisen wrote: >> Except that the Itanium doesn't really outperform 'standard' PC cpus on >> SpecInt, only on FP stuff, and barely there as well. > > How does the Itanium compare in terms of SpecInts PER GHz? Who is silly enough to care anymore ? per-$, per-watt, per-inch-of-rack: all that matters. Per-GHz, no one cares. Heck, any competent processor architect can deliver almost any "SpecInts per GHz" you want: just design the processor to run at only fractional Hz. -- Dennis M. O'Connor dmoc(a)primenet.com |