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From: jb on 2 Jun 2010 15:23
>
>Can anyone confirm or dispute it the relative quality of Actel tools?
>Am I mistaken about them?
>
>Rick
>

I've not used a wide range of FPGA tool suites, just the other major two,
but I have found that Actel's, have been the worst yet.

I don't do very large of complex designs, just stuff for single FPGAs, and
don't really play with the complex features of the suite, so I can't
comment on those areas (where they might actually impress).

The silver lining is that they are in bed with Synplify/Synopsys so you get
that for synthesis, but the pain starts with their layout backend tool.

I run everything Ubuntu GNU/Linux, and prefer batch-mode to a GUI
interface. This in itself is a fair challenge, you must export
LD_LIBRARY_PATHs whenever you run any of their tools (not so bad, I
guess.... but why the need?!) They're painful to use, too, in whenever you
launch a tool, there's about 5 minutes of it sitting there doing nothing,
as far as I can tell. This is really productive when all you need to do is
check if changes to a PDC are OK.

A place-and-route run always leaves my machine reeling for memory
afterwards, it somehow manages to chew through a couple of gig of RAM and
even make things start swapping. I'm convinced there's several memory
holes, but don't have the will to run this behemoth in valgrind.

Their tools take far longer than any other vendors for the same size design
on a similar-sized FPGA, and then you have the issue of any net with fanout
> ~10 resulting in large net delays, so their performance is always
underwhelming.

So on the whole I find using the Libero/Designer suite is never the
highlight of my day.



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From: cfelton on 3 Jun 2010 11:51
>rickman wrote:
>> Can anyone confirm or dispute it the relative quality of Actel tools?
>> Am I mistaken about them?
>
>I am speaking only about my own personal point of view of mine...
>and under Windows (have not yet had time to re-try under Fedora)
>
>The Actel tools take a while to get used too,
>like most big SW suites. It's its own world...
>It is not particularly terrible, I can do
>mostly what I want, inside the bounds of reality
>and the target chip's capacity.
>
>

I have had similar experience. I try to keep my flow tool independent in
this process Actel tools are ok. I can take my design, add the files,
synthesize, PAR, and create a config file. I have not had a reason to use
any of the additional tools and have not run into any major issues.

The learning curve for me was roughly the same as ISE or Quartus. Possibly
a little less because of prior experience with other tools.

chris

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