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From: solomon Alemu on 5 Apr 2010 02:23
I have tried to convert the following verilog code manually in to
VHDL in order to use it in my project which is written in vhdl. But I
am not able to get the same RTL results. Would you help me in
converting the next module or tell me how to instantiate vhdl into
verilog please?

thanks in advance

=======Verilog code=========
`timescale 1ns / 1ps

module ac97 (ready,
command_address, command_data, command_valid,
left_data, left_valid,
right_data, right_valid,
left_in_data, right_in_data,
ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, reset
);

output ready;
input [7:0] command_address;
input [15:0] command_data;
input command_valid;
input [19:0] left_data, right_data;
input left_valid, right_valid;
output [19:0] left_in_data, right_in_data;

input ac97_sdata_in;
input ac97_bit_clock, reset;
output ac97_sdata_out;
output ac97_synch;

reg ready;

reg ac97_sdata_out;
reg ac97_synch;

reg [7:0] bit_count;

reg [19:0] l_cmd_addr;
reg [19:0] l_cmd_data;
reg [19:0] l_left_data, l_right_data;
reg l_cmd_v, l_left_v, l_right_v;
reg [19:0] left_in_data, right_in_data;


always @(posedge ac97_bit_clock) begin
// Generate the sync signal
if (reset) begin
ready <= 1'b0;
// synthesis attribute init of ready is "0";
ac97_sdata_out <= 1'b0;
// synthesis attribute init of ac97_sdata_out is "0";
ac97_synch <= 1'b0;
// synthesis attribute init of ac97_synch is "0";
bit_count <= 8'h00;
// synthesis attribute init of bit_count is "0000";
l_cmd_v <= 1'b0;
// synthesis attribute init of l_cmd_v is "0";
l_left_v <= 1'b0;
// synthesis attribute init of l_left_v is "0";
l_right_v <= 1'b0;
// synthesis attribute init of l_right_v is "0";
end
else begin
if (bit_count == 255)
ac97_synch <= 1'b1;
if (bit_count == 15)
ac97_synch <= 1'b0;
// Generate the ready signal
if (bit_count == 128)
ready <= 1'b1;
if (bit_count == 2)
ready <= 1'b0;

// Latch user data at the end of each frame. This ensures that the
// first frame after reset will be empty.
if (bit_count == 255)
begin
l_cmd_addr <= {command_address, 12'h000};
l_cmd_data <= {command_data, 4'h0};
l_cmd_v <= command_valid;
l_left_data <= left_data;
l_left_v <= left_valid;
l_right_data <= right_data;
l_right_v <= right_valid;
end

if ((bit_count >= 0) && (bit_count <= 15))
// Slot 0: Tags
case (bit_count[3:0])
4'h0: ac97_sdata_out <= 1'b1; // Frame valid
4'h1: ac97_sdata_out <= l_cmd_v; // Command address valid
4'h2: ac97_sdata_out <= l_cmd_v; // Command data valid
4'h3: ac97_sdata_out <= l_left_v; // Left data valid
4'h4: ac97_sdata_out <= l_right_v; // Right data valid
default: ac97_sdata_out <= 1'b0;
endcase

else if ((bit_count >= 16) && (bit_count <= 35))
// Slot 1: Command address (8-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_addr[35-bit_count] : 1'b0;

else if ((bit_count >= 36) && (bit_count <= 55))
// Slot 2: Command data (16-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_data[55-bit_count] : 1'b0;

else if ((bit_count >= 56) && (bit_count <= 75))
begin
// Slot 3: Left channel
ac97_sdata_out <= l_left_v ? l_left_data[19] : 1'b0;
l_left_data <= { l_left_data[18:0], l_left_data[19] };
end
else if ((bit_count >= 76) && (bit_count <= 95))
// Slot 4: Right channel
ac97_sdata_out <= l_right_v ? l_right_data[95-bit_count] : 1'b0;
else
ac97_sdata_out <= 1'b0;

bit_count <= bit_count+1;
end
end // always @ (posedge ac97_bit_clock)

always @(negedge ac97_bit_clock) begin
if ((bit_count >= 57) && (bit_count <= 76))
// Slot 3: Left channel
left_in_data <= { left_in_data[18:0], ac97_sdata_in };
else if ((bit_count >= 77) && (bit_count <= 96))
// Slot 4: Right channel
right_in_data <= { right_in_data[18:0], ac97_sdata_in };
end
endmodule



From: Jonathan Bromley on 5 Apr 2010 03:58
On Sun, 4 Apr 2010 23:23:33 -0700 (PDT), solomon Alemu
<soloalemu(a)gmail.com> wrote:

> I have tried to convert the following verilog code manually in to
>VHDL in order to use it in my project which is written in vhdl. But I
>am not able to get the same RTL results. Would you help me in
>converting the next module or tell me how to instantiate vhdl into
>verilog please?

The code you posted looks like clean synchronous RTL,
and therefore it should be very easy to translate
into VHDL. The one possible problem is your use of
synthesis attributes - you will need to look at the tool
documentation to see how to write them in VHDL - if they
are really necessary, which I doubt.

Could you indicate what you mean by "not able to get
the same RTL results"? You can't expect tools to give
exactly the same gate-level results from two different
but functionally identical pieces of code, but that is
presumably not a problem.

Instantiation of Verilog into VHDL is usually OK but
there are many tool-dependent details. The FPGA
synthesis tools usually do it without a murmur - have
you tried? - but simulation can be a little more
troublesome. The most common problem is case
sensitivity (Verilog is case-sensitive, VHDL is not)
and keyword clashes. I don't think you have any
keyword problems here, and the names are consistetly
lower-case, so that should all be OK.

PLease come back if you have any specific issues with
the translation, but I'm not going to do it all for you:-)

>=======Verilog code=========
[snipped]

--
Jonathan Bromley
From: Gabor on 5 Apr 2010 09:28
On Apr 5, 2:23 am, solomon Alemu <soloal...(a)gmail.com> wrote:
>   I have tried to convert the following verilog code  manually in to
> VHDL  in order to use it in my project which is written in vhdl. But I
> am not able to get the same RTL results. Would you help me in
> converting the next module or tell me how to instantiate vhdl into
> verilog please?
>
> thanks in advance
>
> =======Verilog code=========
[snip]

Xilinx ISE has a tool called "View HDL instantiation template"
which automatically produced this VHDL instantiation you can
cut and paste in your top level:


-- VHDL Instantiation Created from source file ac97.v -- 09:23:22
04/05/2010
--
-- Notes:
-- 1) This instantiation template has been automatically generated
using types
-- std_logic and std_logic_vector for the ports of the instantiated
module
-- 2) To use this template to instantiate this entity, cut-and-paste
and then edit

COMPONENT ac97
PORT(
command_address : IN std_logic_vector(7 downto 0);
command_data : IN std_logic_vector(15 downto 0);
command_valid : IN std_logic;
left_data : IN std_logic_vector(19 downto 0);
left_valid : IN std_logic;
right_data : IN std_logic_vector(19 downto 0);
right_valid : IN std_logic;
ac97_sdata_in : IN std_logic;
ac97_bit_clock : IN std_logic;
reset : IN std_logic;
ready : OUT std_logic;
left_in_data : OUT std_logic_vector(19 downto 0);
right_in_data : OUT std_logic_vector(19 downto 0);
ac97_sdata_out : OUT std_logic;
ac97_synch : OUT std_logic
);
END COMPONENT;

Inst_ac97: ac97 PORT MAP(
ready => ,
command_address => ,
command_data => ,
command_valid => ,
left_data => ,
left_valid => ,
right_data => ,
right_valid => ,
left_in_data => ,
right_in_data => ,
ac97_sdata_out => ,
ac97_sdata_in => ,
ac97_synch => ,
ac97_bit_clock => ,
reset =>
);

As you can see, it has a nasty habit of ignoring your original
order of ports and placing inputs first, but it saves some
time, especially if you're not fluent in Verilog.

HTH,
Gabor
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