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From: Svenn Are Bjerkem on 19 Oct 2009 08:56
Hi,
trying to debug a design and look for a way to inspect the actual data
that are inside a FIFO which has been generated with the core
generator. I have turned off all optimization in order to see process
variables etc., but all I find is a lot of control signals and
generics. I looked into the behavioural code and found that the fifo
is implemented as a linked list. I wonder if anybody in the group has
been successful in looking at the data stream passing through. I was
hoping for a nice std_logic_vector, but obviously this is not the
case. (At least from what I find)

Modelsim 6.4 and VHDL with ISE 10.3

--
Svenn
From: maxascent on 19 Oct 2009 09:08
Not sure about FIFOs but with Xilinx block ram you can just go to the
Modelsim memory window and look at the contents.

Jon

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From: Gabor on 19 Oct 2009 09:28
On Oct 19, 8:56 am, Svenn Are Bjerkem <svenn.bjer...(a)googlemail.com>
wrote:
> Hi,
> trying to debug a design and look for a way to inspect the actual data
> that are inside a FIFO which has been generated with the core
> generator. I have turned off all optimization in order to see process
> variables etc., but all I find is a lot of control signals and
> generics. I looked into the behavioural code and found that the fifo
> is implemented as a linked list. I wonder if anybody in the group has
> been successful in looking at the data stream passing through. I was
> hoping for a nice std_logic_vector, but obviously this is not the
> case. (At least from what I find)
>
> Modelsim 6.4 and VHDL with ISE 10.3
>
> --
> Svenn

It sounds like Core Generator has given you the "Behavioral" model
which is not cycle accurate. In fact at time zero you should get
a warning to this effect. If you want to dig into FIFO internals
you'll need the structural model, which you can generate by setting
your CoreGen project options. Even then it may be difficult to
see what's in the FIFO. If you're willing to believe that the
CoreGen FIFO just works, you can build a very simple FIFO model
and hook it up in parallel to the CoreGen FIFO and inspect what
is in your model. Just be sure to only write to your model when the
CoreGen reports not full and only read when CoreGen reports not empty.
This and a common reset should keep the models in sync and you can
easily inspect the contents of your model.

Regards,
Gabor
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