Prev: SP601 HDL source files available?
Next: Very interesting finding about V4 CLB configuration bits
From: Cyrille_ on 29 Sep 2009 12:16 Can we program a bitstream in the Daughter Board Spartan 3 of the Altium nanoboard with Xilinx impact instead of Altium Designer ? If yes, which JTAG must be used with which connectors ? I have read interesting stuff on that subject here : http://wiki.altium.com/display/ADOH/Updating+the+Firmware+on+the+Desktop+NanoBoard+NB2DSK01 I copy/paste : If you have an older, Altium Universal JTAG Interface, use this to connect from the parallel port on your PC to the 'SYSTEM JTAG' header. Note that the selector switch on the Universal JTAG Interface is used only when programming a JTAG device from Altera Quartus II or Xilinx ISE tools directly, and via their associated parallel cabling. The switch position has no relevance when programming the Configuration PROM from Altium Designer. and there : http://www.altium.com/files/pdfs/Connecting-the-Universal-JTAG-Interface-to-the-Altium-NanoBoard-NB1.pdf But I need more informations ... Thanks in advance, Cyrille
From: Alex Freed on 29 Sep 2009 17:13 Cyrille_ wrote: > Can we program a bitstream in the Daughter Board Spartan 3 of the Altium > nanoboard with Xilinx impact instead of Altium Designer ? > If yes, which JTAG must be used with which connectors ? Use a flat ribbon cable to connect the NanoBoard to a printer port. It will look like a parallel cable III to the PC. Then you can use iMPACT to program the Daughter Board. The "system JTAG" connector is intended for reprogramming the FPGA on the main board, not the Daughter Board. -Alex.
From: Cyrille_ on 2 Oct 2009 11:24 Thanks for your response. Finally, I have found a solution for my problem without use Impact. I explain for those who don't know this solution : - Download Xilinx bitstream to Flah memory SD Card with Altium Designer - bootstrap the daughter board FPGA from SD Card It explains in the following document "TR0149 Technical Reference for Altium's Xilinx Spartan-3 Daughter Board DB30.pdf" p68. I haven't tested it yet but I think it works. Cyrille Chevrot --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
|
Pages: 1 Prev: SP601 HDL source files available? Next: Very interesting finding about V4 CLB configuration bits |