I'd rather switch than fight!
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From: Jonathan Bromley on 9 Apr 2010 15:07 On Apr 9, 3:07 pm, rickman <gnu...(a)gmail.com> wrote: > I think I have about had it with VHDL. I've been using the > numeric_std library and eventually learned how to get around the > issues created by strong typing although it can be very arcane at > times. I have read about a few suggestions people are making to help > with some aspects of the language, like a selection operator like > Verilog has. But it just seems like I am always fighting some aspect > of the VHDL language. > > I guess part of my frustration is that I have yet to see where strong > typing has made a real difference in my work... at least an > improvement. I think Andy has it about right. If you think signed arithmetic was a tad messy in VHDL, wait until you find how successfully you can be screwed by Verilog. The really cool thing is that Verilog is polite, and doesn't tell you when it's screwing you. At least VHDL is up-front about it. How many times have you created a design in VHDL that got through compilation, but was broken in a surprising way that was directly related to a quirk of the language? Betcha you can count the occurrences on one hand. Verilog does that to you all the time; it has startlingly weak compile-time checking, and only slightly stronger elaboration-time checking. How comfortable are you with most-significant bits being silently lost when you copy a wide vector into a narrow one? How about signed values being silently zero-filled to the width of a wider target? > My customer uses Verilog and has mentioned several times > how he had tried using VHDL and found it too arcane to bother with. > He works on a much more practical level than I often do and it seems > to work well for him. Is "practical" here a euphemism? > One of my goals over the summer is to teach myself Verilog so that I > can use it as well as I currently use VHDL. Then I can make a fully > informed decision about which I will continue to use. I'd appreciate > pointers on good references, web or printed. Good luck. As I've pointed out on many occasions, the textbook situation is much less satisfactory for Verilog than it is for VHDL. Whatever you do, PLEASE get yourself a copy of Sutherland's Verilog Gotchas book (much of it is available free online). You may not understand all of it at first, but you sure will want to revisit it later. It's just a pity that it's incomplete and doesn't cover ALL the many ways in which Verilog can silently mess you up. To be serious for a moment: a training class from a reputable independent provider will save you a ton of money in the long run. Your time is valuable. > Without starting a major argument, anyone care to share their feelings > on the differences in the two languages? Errrrm, I think I just did. -- Jonathan Bromley
From: Nico Coesel on 9 Apr 2010 15:31 rickman <gnuarm(a)gmail.com> wrote: >I think I have about had it with VHDL. I've been using the >numeric_std library and eventually learned how to get around the >issues created by strong typing although it can be very arcane at >times. I have read about a few suggestions people are making to help >with some aspects of the language, like a selection operator like >Verilog has. But it just seems like I am always fighting some aspect >of the VHDL language. > >I guess part of my frustration is that I have yet to see where strong >typing has made a real difference in my work... at least an I also write a lot of C. Over the past years I've noticed that C compilers (GCC to be exact) have become much more strict when it comes to type checking. No more automatic casting. I'm sure this is done for a good reason! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) --------------------------------------------------------------
From: Patrick Maupin on 9 Apr 2010 16:05 On Apr 9, 2:07 pm, Jonathan Bromley <s...(a)oxfordbromley.plus.com> wrote: > > I guess part of my frustration is that I have yet to see where strong > > typing has made a real difference in my work... at least an > > improvement. > > I think Andy has it about right. If you think signed arithmetic > was a tad messy in VHDL, wait until you find how successfully you > can be screwed by Verilog. The really cool thing is that Verilog > is polite, and doesn't tell you when it's screwing you. At least > VHDL is up-front about it. How many times have you created a > design in VHDL that got through compilation, but was broken in > a surprising way that was directly related to a quirk of the > language? Betcha you can count the occurrences on one hand. > Verilog does that to you all the time; it has startlingly > weak compile-time checking, and only slightly stronger > elaboration-time checking. > > How comfortable are you with most-significant bits being > silently lost when you copy a wide vector into a narrow > one? How about signed values being silently zero-filled > to the width of a wider target? Personally? Very. As the proponents of agile programming languages (I love Python) will point out, the sort of typing errors that you are describing are but a small subset of the ways you can screw up your design. Any reasonable testbench will find these issues. And BTW, (IMO) it's *much* easier to code a reasonable testbench in verilog than in VHDL. But, obviously, your mileage varies. Regards, Pat
From: Patrick Maupin on 9 Apr 2010 16:16 On Apr 9, 2:31 pm, n...(a)puntnl.niks (Nico Coesel) wrote: > I also write a lot of C. Over the past years I've noticed that C > compilers (GCC to be exact) have become much more strict when it comes > to type checking. No more automatic casting. I'm sure this is done for > a good reason! I used to write a lot of Modula-2. It was much better than (pre-ANSI) C (and in fact was one of the contenders for the language the DOD uses as ADA now, which is what VHDL was based on). IMO, Modula-2 was at a sweet spot on verbosity vs. checking. But then ANSI C came along, and was "good enough". Combine that with the compilers getting smart enough to let you know about potential pitfalls, and there wasn't much room for another language in the ecological niche that C fills, and, for example, the Modula-2 ecosystem dwindled to nothing, and the Ada ecosystem limped along, primarily propped up by the DOD and educational institutions. I think there really is a good corollary with HDLs there -- Verilog synthesizers and simulators have a lot of options for telling you about warnings and things, and Verilog occupies the same sort of sweet spot as C, with only a few people preferring Ada or VHDL over C or Verilog. Regards, Pat
From: -jg on 10 Apr 2010 19:06
On Apr 10, 2:07 am, rickman <gnu...(a)gmail.com> wrote: > One of my goals over the summer is to teach myself Verilog so that I > can use it as well as I currently use VHDL. Then I can make a fully > informed decision about which I will continue to use. I'd appreciate > pointers on good references, web or printed. You could also look at Jan Decaluwe's MyHDL ? http://www.myhdl.org/doku.php and a case example here : http://www.jandecaluwe.com/hdldesign/digmac.html this allows you to go in either direction, to VHDL to Verilog, and to 'test early'. -jg |