I'd rather switch than fight!
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From: rickman on 20 Apr 2010 16:44 On Apr 17, 7:17 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > In comp.arch.fpga rickman <gnu...(a)gmail.com> wrote: > (snip on test benches) > > >> I suppose so, but consider it the other way around. > >> If your test bench is good enough then it will catch all static > >> timing failures (eventually). ?With static timing analysis, there > >> are many things that you don't need to check with the test bench. > > I don't follow what you are saying. This first sentence seems to be > > saying that a timing simulation *is* a good place to find timing > > problems, or are you talking about real world test benches? The point > > is that static timing is enough to catch all timing failures given > > that your timing constraints cover the design properly... and I agree > > that is a big given. Your second sentence seems to be agreeing with > > my previous statement. > > Yes, I was describing real world (hardware) test benches. > > Depending on how close you are to a setup/hold violation, > it may take a long time for a failure to actually occur. That is the point. Finding timing violations in a simulation is hard, finding them in physical hardware is not possible to do with any certainty. A timing violation depends on the actual delays on a chip and that will vary with temperature, power supply voltage and process variations between chips. I had to work on a problem design once because the timing analyzer did not work or the constraints did not cover (I firmly believe it was the tools, not the constraints since it failed on a number of different designs). We tried finding the chip that failed at the lowest temperature and then used that at an elevated temperature for our "final" timing verification. Even with that, I had little confidence that the design would never have a problem from timing. Of course on top of that the chip was being used at 90% capacity. This design is the reason I don't work for that company anymore. The section head knew about all of these problems before he assigned the task and then expected us to work 70 hour work weeks. At least we got them to buy us $100 worth of dinner each evening! The point is that if you don't do static timing analysis (or have an analyzer that is broken) timing verification is nearly impossible. > >> Also, you can't do static timing analysis on the implemented logic. > >> (That is, given an actual built circuit and a logic analyzer.) > > So? > >> Now, setup and hold violations are easy to test with static > >> analysis, but much harder to check in actual logic. ?Among others, > >> you would want to check all possible clock skew failures, which is > >> normally not possible. ?With the right test bench and logic > >> implementation (including programmable delays on each FF clock) > >> it might be possible, though. > > In twenty years of designing with FPGAs I have never found a clock > > skew problem. I always write my code to allow the clock trees to > > deliver the clocks and I believe the tools guaranty that there will > > not be a skew problem. Static timing actually does cover clock skew, > > at least the tools I use. > > Yes, I was trying to cover the case of not using static timing > analysis but only testing actual hardware. For ASICs, it is > usually necessary to test the actual chips, though they should > have already passed static timing. If you find a timing bug in the ASIC chip, isn't that a little too late? Do you test at elevated temperature? Do you generate special test vectors? How is this different from just testing the logic? > > BTW, how do you design a "right test bench"? Static timing analysis > > will at least give you the coverage level although one of my > > complaints is that they don't provide any tools for analyzing if your > > constraints are correct. But I have no idea how to verify that my > > test bench is testing the timing adequately. > > If you only have one clock, it isn't so hard. As you add more, > with different frequencies and/or phases, it gets much harder, > I agree. It would be nice to get as much help as possible > from the tools. The number of clocks is irrelevant. I don't consider timing issues of crossing clock domains to be "timing" problems. There you can only solve the problem with proper logic design, so it is a logic problem. Rick
From: Patrick Maupin on 20 Apr 2010 17:44 On Apr 16, 4:38 am, David Brown <da...(a)westcontrol.removethisbit.com> wrote: > The old joke about Ada is that when you get your code to compile, it's > ready to ship. I certainly wouldn't go that far, but testing is > something you do in cooperation with static checking, not as an alternative. GOOD static checking tools are great (and IMHO part of a testbench). I certainly hope you're not trying to imply that the typechecking built into VHDL is a substitute for a good model checker! Regards, Pat
From: Patrick Maupin on 20 Apr 2010 17:46 On Apr 10, 8:21 pm, Jan Decaluwe <jandecal...(a)gmail.com> wrote: > On Apr 9, 6:53 pm, Patrick Maupin <pmau...(a)gmail.com> wrote: > > > > > On Apr 9, 9:07 am, rickman <gnu...(a)gmail.com> wrote: > > > > I think I have about had it with VHDL. I've been using the > > > numeric_std library and eventually learned how to get around the > > > issues created by strong typing although it can be very arcane at > > > times. I have read about a few suggestions people are making to help > > > with some aspects of the language, like a selection operator like > > > Verilog has. But it just seems like I am always fighting some aspect > > > of the VHDL language. > > > > I guess part of my frustration is that I have yet to see where strong > > > typing has made a real difference in my work... at least an > > > improvement. My customer uses Verilog and has mentioned several times > > > how he had tried using VHDL and found it too arcane to bother with. > > > He works on a much more practical level than I often do and it seems > > > to work well for him. > > > > One of my goals over the summer is to teach myself Verilog so that I > > > can use it as well as I currently use VHDL. Then I can make a fully > > > informed decision about which I will continue to use. I'd appreciate > > > pointers on good references, web or printed. > > > > Without starting a major argument, anyone care to share their feelings > > > on the differences in the two languages? > > > > Rick > > > The best online references are the Sutherland Verilog references. > > There is an online HTML reference for Verilog 95 (excellent), and a > > PDF for Verilog 2001 (good): > > >http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.h....... > > > Cliff Cummings has a lot of good papers on Verilog at his site: > > >http://sunburst-design.com/papers/ > > > In particular, if you read and carefully grok his paper about non- > > blocking vs. blocking assignments, you will be well on your way to > > being a Verilog wizard: > > >http://sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf > > The infamous Guideline #5 bans variable semantics from always blocks > with sequential logic. It must be the Worst Guideline ever for RTL > designers. > The result is not wizardry but ignorance. > > How are we supposed to "raise the abstraction level" if Verilog RTL > designers > can't even use variables? I didn't notice this post until today. I think you are completely misreading the guidelines if you think they mean "Verilog RTL designers can't even use variables" Regards, Pat
From: glen herrmannsfeldt on 20 Apr 2010 17:56 In comp.arch.fpga rickman <gnuarm(a)gmail.com> wrote: > On Apr 17, 7:17?pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: (snip on test benches) >> Yes, I was describing real world (hardware) test benches. >> Depending on how close you are to a setup/hold violation, >> it may take a long time for a failure to actually occur. > That is the point. Finding timing violations in a simulation is hard, > finding them in physical hardware is not possible to do with any > certainty. A timing violation depends on the actual delays on a chip > and that will vary with temperature, power supply voltage and process > variations between chips. But they have to be done for ASICs, and all other chips as part of the fabrication process. For FPGAs you mostly don't have to do such, relying on the specifications and that the chips were tested appropriately in the factory. > I had to work on a problem design once > because the timing analyzer did not work or the constraints did not > cover (I firmly believe it was the tools, not the constraints since it > failed on a number of different designs). We tried finding the chip > that failed at the lowest temperature and then used that at an > elevated temperature for our "final" timing verification. Even with > that, I had little confidence that the design would never have a > problem from timing. Of course on top of that the chip was being used > at 90% capacity. This design is the reason I don't work for that > company anymore. The section head knew about all of these problems > before he assigned the task and then expected us to work 70 hour work > weeks. At least we got them to buy us $100 worth of dinner each > evening! One that I worked with, though not at all at that level, was a programmable ASIC (for a systolic array processor). For some reason that I never knew the timing was just a little bit off regarding to writes to the internal RAM. The solution was to use two successive writes, which seemed to work. In the usual operation mode, the RAM was initialized once, so the extra cycle wasn't much of a problem. There were also some modes where the RAM had to be written while processing data, such that the extra cycle meant that the processor ran that much slower. > The point is that if you don't do static timing analysis (or have an > analyzer that is broken) timing verification is nearly impossible. And even if you do, the device might still have timing problems. (snip) >> Yes, I was trying to cover the case of not using static timing >> analysis but only testing actual hardware. ?For ASICs, it is >> usually necessary to test the actual chips, though they should >> have already passed static timing. ? > If you find a timing bug in the ASIC chip, isn't that a little too > late? Do you test at elevated temperature? Do you generate special > test vectors? How is this different from just testing the logic? It might be that it works at a lower clock rate, or other workarounds can be used. Yes, it is part of testing the logic. (snip) >> If you only have one clock, it isn't so hard. ?As you add more, >> with different frequencies and/or phases, it gets much harder, >> I agree. ?It would be nice to get as much help as possible >> from the tools. > The number of clocks is irrelevant. I don't consider timing issues of > crossing clock domains to be "timing" problems. There you can only > solve the problem with proper logic design, so it is a logic > problem. Yes, there is nothing to do about asynchronous clocks. It just has to work in all cases. But in the case of supposedly related clocks, you have to verify it. There are designs that have one clock a multiple of the other clock frequency, or multiple phases with specified timing relationship. Or even single clocks with specified duty cycle. (I still remember the 8086 with its 33% duty cycle clock.) With one clock you can run combinations of voltage, temperature, and clock rate, not so hard but still a lot of combinations. With related clocks, you have to verify that the timing between the clocks works. -- glen
From: Jan Decaluwe on 20 Apr 2010 18:14
On Apr 20, 11:46 pm, Patrick Maupin <pmau...(a)gmail.com> wrote: > On Apr 10, 8:21 pm, Jan Decaluwe <jandecal...(a)gmail.com> wrote: > > > > > On Apr 9, 6:53 pm, Patrick Maupin <pmau...(a)gmail.com> wrote: > > > > On Apr 9, 9:07 am, rickman <gnu...(a)gmail.com> wrote: > > > > > I think I have about had it with VHDL. I've been using the > > > > numeric_std library and eventually learned how to get around the > > > > issues created by strong typing although it can be very arcane at > > > > times. I have read about a few suggestions people are making to help > > > > with some aspects of the language, like a selection operator like > > > > Verilog has. But it just seems like I am always fighting some aspect > > > > of the VHDL language. > > > > > I guess part of my frustration is that I have yet to see where strong > > > > typing has made a real difference in my work... at least an > > > > improvement. My customer uses Verilog and has mentioned several times > > > > how he had tried using VHDL and found it too arcane to bother with. > > > > He works on a much more practical level than I often do and it seems > > > > to work well for him. > > > > > One of my goals over the summer is to teach myself Verilog so that I > > > > can use it as well as I currently use VHDL. Then I can make a fully > > > > informed decision about which I will continue to use. I'd appreciate > > > > pointers on good references, web or printed. > > > > > Without starting a major argument, anyone care to share their feelings > > > > on the differences in the two languages? > > > > > Rick > > > > The best online references are the Sutherland Verilog references. > > > There is an online HTML reference for Verilog 95 (excellent), and a > > > PDF for Verilog 2001 (good): > > > >http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.h....... > > > > Cliff Cummings has a lot of good papers on Verilog at his site: > > > >http://sunburst-design.com/papers/ > > > > In particular, if you read and carefully grok his paper about non- > > > blocking vs. blocking assignments, you will be well on your way to > > > being a Verilog wizard: > > > >http://sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf > > > The infamous Guideline #5 bans variable semantics from always blocks > > with sequential logic. It must be the Worst Guideline ever for RTL > > designers. > > The result is not wizardry but ignorance. > > > How are we supposed to "raise the abstraction level" if Verilog RTL > > designers > > can't even use variables? > > I didn't notice this post until today. I think you are completely > misreading the guidelines if you think they mean "Verilog RTL > designers can't even use variables" I use that line as a shorthand for "Guideline #5 combined with Guideline #1, if taken seriously, forbids the use of traditional variable semantics provided by blocking assignments, in the context of a clocked always block". No matter how absurd I hope this sounds to you, that's really what it says. Jan |