ISE Design Suite 11 will not evaluate 2's comp
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From: shannon on 3 Jun 2010 13:47 If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! According to this information [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] ISE 11 should be running verilog 2001, however when I try to run the arithmetic shift ">>>" it does not populate 1's for negative numbers as it should. Does anyone have any advice on how to correct this problem? --------------------------------------- Posted through http://www.FPGARelated.com |