ISE Design Suite 11 will not evaluate 2's comp
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From: shannon on 3 Jun 2010 15:21 If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! According to this information [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] ISE 11 should be running verilog 2001, however when I try to run the arithmetic shift ">>>" it does not populate 1's for negative numbers as it should. Does anyone have any advice on how to correct this problem? --------------------------------------- Posted through http://www.FPGARelated.com
From: Gabor on 3 Jun 2010 15:47 On Jun 3, 1:48 pm, "shannon" <sesilver(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! > > According to this information > [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] > ISE 11 should be running verilog 2001, however when I try to run the > arithmetic shift ">>>" it does not populate 1's for negative numbers as it > should. > > Does anyone have any advice on how to correct this problem? > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com There was a thread on this topic in comp.lang.verilog You can always work around the problem using >> like: reg [15:0] signed_vector; .. . . some_vector <= {16{signed_vector[15]},signed_vector} >> shift_val; (where shift_val is less than or equal to 16) .. . . to copy the MSB as you shift right. Did you check if this was fixed in 12.1? Regards, Gabor
From: Jonathan Bromley on 3 Jun 2010 16:38
On Thu, 03 Jun 2010 12:47:14 -0500, "shannon" <sesilver(a)n_o_s_p_a_m.gmail.com> wrote: >If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! > >According to this information >[link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] >ISE 11 should be running verilog 2001, however when I try to run the >arithmetic shift ">>>" it does not populate 1's for negative numbers as it >should. > >Does anyone have any advice on how to correct this problem? Yup. 1) Try the code in a reputable simulator. If the simulator gives sign extension and Xilinx doesn't, report the bug to Xilinx. 2) Assuming (much the most likely scenario) that you did (1) and discovered that the simulator, too, did an unsigned right shift, blush temporarily and then recognise that signed arithmetic in Verilog-2001 is not to be taken lightly. It is full of obscure and counter-intuitive traps, and you wouldn't be the first person to fall headlong into them. Read my post in http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/549b3d83f7e1fb11/ for much more detail. After reading that stuff, come back here with the *exact* code (including declarations) if you still think the tool is at fault. -- Jonathan Bromley |