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From: Jason Thibodeau on 23 Mar 2010 20:26
As I mentioned in another message, I am attempting to implement an IWLS
benchmark on a spartan3e. I wrote definitions for all the undefined
gates, and it now synthesizes just fine.

However, I am attempting to manually place and route some main blocks in
the design. When I go into PlanAhead, I do not see my benchmark listed
in the primitives. This benchmark has an lfsr feeding it (the lfsr is
also not able to be seen in PlanAhead), and the ourputs are tied to a
signal, but are not tied to pins on the fpga.

What am I doing wrong?
--
Jason Thibodeau
From: Jason Thibodeau on 24 Mar 2010 13:42
On 03/23/2010 08:26 PM, Jason Thibodeau wrote:
> As I mentioned in another message, I am attempting to implement an IWLS
> benchmark on a spartan3e. I wrote definitions for all the undefined
> gates, and it now synthesizes just fine.
>
> However, I am attempting to manually place and route some main blocks in
> the design. When I go into PlanAhead, I do not see my benchmark listed
> in the primitives. This benchmark has an lfsr feeding it (the lfsr is
> also not able to be seen in PlanAhead), and the ourputs are tied to a
> signal, but are not tied to pins on the fpga.
>
> What am I doing wrong?

I think i figured it out. If the outputs to the benchmark are not
routed, the gates are being optimized out. I assigned the output vector
to an output on the chip (while not actually assigning pins), and all
the instances showed up after synthesis.

--
Jason Thibodeau
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