From: glen herrmannsfeldt on
Manmohan <mmmmec(a)gmail.com> wrote:
(snip)

> Hi Thank you for the reply... But actually I am planning to implement
> a single set of 8 bit wide bus for both input and output direction....
> So , I need to have a bidirectional bus .... Is there any other way
> other than tristating to implement such a bus ?

As far as I know, the synthesis tools will generate an emulated
tristate bus. One can imagine a combination of AND/OR logic that,
as long as only one enable is active, generates the expected result.
In addition, it doesn't fail if other than one enable is active.

The problem is, that as chips get bigger it is necessary to
buffer the interconnect lines, which you can't do if you don't
know the direction. Even if the signal has to go twice as far
(which it may have to do) it is still faster.

-- glen
From: RCIngham on
>
>I would like to know if there is any other way to implement a
>bidirectional bus that does not use the IOBs ?
>

Although internal tristate busses are not unusual in ASICs (though some
vendors have deprecated them at some periods because of the bad effects of
floating signals inside ICs), they are not really compatible with FPGA
technology. Just don't do it! Please!

There's lots of routing resource in V4 FPGAs, so a conventional crosspoint
bus structure should work fine.


---------------------------------------
Posted through http://www.FPGARelated.com
From: Manmohan on
On Apr 14, 5:18 pm, "RCIngham"
<robert.ingham(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> >I would like to know if there is any other way to implement a
> >bidirectional bus that does not use the IOBs ?
>
> Although internal tristate busses are not unusual in ASICs (though some
> vendors have deprecated them at some periods because of the bad effects of
> floating signals inside ICs), they are not really compatible with FPGA
> technology. Just don't do it! Please!
>
> There's lots of routing resource in V4 FPGAs, so a conventional crosspoint
> bus structure should work fine.
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

So does this mean that it is possible to have bidirectional buses
inside the FPGA without using the tristate logic from the IOBs?
From: RCIngham on
>On Apr 14, 5:18=A0pm, "RCIngham"
><robert.ingham(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
>> >I would like to know if there is any other way to implement a
>> >bidirectional bus that does not use the IOBs ?
>>
>> Although internal tristate busses are not unusual in ASICs (though some
>> vendors have deprecated them at some periods because of the bad effects
o=
>f
>> floating signals inside ICs), they are not really compatible with FPGA
>> technology. Just don't do it! Please!
>>
>> There's lots of routing resource in V4 FPGAs, so a conventional
crosspoin=
>t
>> bus structure should work fine.
>>
>> --------------------------------------- =A0 =A0 =A0 =A0
>> Posted throughhttp://www.FPGARelated.com
>
>So does this mean that it is possible to have bidirectional buses
>inside the FPGA without using the tristate logic from the IOBs?

Separate buses for each direction.

The Wishbone Bus is a good example of this:
www.opencores.org/downloads/wbspec_b3.pdf


---------------------------------------
Posted through http://www.FPGARelated.com
From: glen herrmannsfeldt on
Manmohan <mmmmec(a)gmail.com> wrote:
(snip)

> So does this mean that it is possible to have bidirectional buses
> inside the FPGA without using the tristate logic from the IOBs?

The IOBs would only work if the bus was external.

You can design with internal tristate, as far as I know,
with most tools, but the implementation is more like a MUX
going into one bus, and then to all inputs driven by the bus.

If I did it, it would be AND gates with one input for the
signal and the other for the enable. Then OR all the AND gate
outputs together, and send that to all inputs reading from the bus.

I don't know if that is how it is implemented, but it could
be done that way. You can also do it yourself.

-- glen
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