Integrated AGC 100kHz-10MHz
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From: Jamie on 29 Nov 2009 14:13 Hammy wrote: > I have a signal between 100kHz to 10MHz sinusoidal DAC output. The > signal starts out at 650mVpp low frequency with a small DC offset of > about 10mV. As the frequency increases the DC offset increases and the > pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to > about 100mVpp with about 500mV DC offset. > > Are there any single chip or small parts count solution AGC that can > maintain a constant 650mVpp output under the above conditions. > > I've been goggling AGC and haven't had much luck other then 100 part > count schematics there must be an integrated version? If sounds like you have a cos/sin of your output shifting amplitude. This would thus be the same as changing the duty cycle and causing the offset you're seeing. I wonder if you have a unity stage for the DAC to prevent excess loading, do to load capacitance ? This all maybe a shot in the dark but it's my shot :)
From: john jardine on 29 Nov 2009 15:38 "Hammy" <spam(a)spam.com> wrote in message news:88v4h55c3d0fj1ilbfh6v41mjkqda0r3j2(a)4ax.com... >I have a signal between 100kHz to 10MHz sinusoidal DAC output. The > signal starts out at 650mVpp low frequency with a small DC offset of > about 10mV. As the frequency increases the DC offset increases and the > pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to > about 100mVpp with about 500mV DC offset. > > Are there any single chip or small parts count solution AGC that can > maintain a constant 650mVpp output under the above conditions. > > I've been goggling AGC and haven't had much luck other then 100 part > count schematics there must be an integrated version? With a 50MHz clock the signal would normally drop to maybe 500mV at 10MHz but that's assuming you're measuring using a 10:1 scope probe with say 13pF tip capacitance. The 'FSadjust' and 'Rset' can be used for AGC. Put a DC 'level set' voltage on the Rser resistor end that normally connects to 0V. (OV=max out). Idea is to throttle the output swing to (say) 1/2 of normal, which then allows a +50% increase to compensate for losses.
From: Hammy on 29 Nov 2009 15:43 On Sun, 29 Nov 2009 09:40:02 -0800, Joerg <invalid(a)invalid.invalid> wrote: > >Yes, but it's expensive: What isn't ;) >http://www.analog.com/static/imported-files/Data_Sheets/AD8367.pdf I was thinking of putting a digital pot in the AD8045 feedback loop. But by the time all is said and done 6 Bucks for the AD8637 looks pretty good.Newark sent me out a 25% off flyer so it's a good time to buy parts. I'm using an AD9834 DDS IC to build my own signal generator controlled from the serial port. The parts pretty impressive for $7 sine, square ,triangle output can perform various modulation with minimal parts ,ability to sweep frequency range defined step size and rate and a 75MHz clock. I know AD make much faster ones but a 10MHz output max is good for me. Trying to keep it in the $35 to $50 range. I was going to buy a cheap $150 - $250 Chinese one but decided to build my own. >If on a budget you could build one around a uA733 or similar chip, add a >simple detector and a FET as the gain control element. If your budget is >super-tight use a dual-gate MOSFET which allows the gain control range >you are looking for. One gate gets the signal, the other the control >voltage. > >Here is another trick to save a buck: Characterize the signal drop >versus frequency. Then use a simple gain control stage and place a 2nd >DAC. This 2nd DAC is used to set the gain control input and is updated >whenever you update the frequency.
From: Hammy on 29 Nov 2009 15:47 On Sun, 29 Nov 2009 20:38:18 -0000, "john jardine" <zen177928(a)zen.co.uk> wrote: > >"Hammy" <spam(a)spam.com> wrote in message >news:88v4h55c3d0fj1ilbfh6v41mjkqda0r3j2(a)4ax.com... >>I have a signal between 100kHz to 10MHz sinusoidal DAC output. The >> signal starts out at 650mVpp low frequency with a small DC offset of >> about 10mV. As the frequency increases the DC offset increases and the >> pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to >> about 100mVpp with about 500mV DC offset. >> >> Are there any single chip or small parts count solution AGC that can >> maintain a constant 650mVpp output under the above conditions. >> >> I've been goggling AGC and haven't had much luck other then 100 part >> count schematics there must be an integrated version? > >With a 50MHz clock the signal would normally drop to maybe 500mV at 10MHz >but that's assuming you're measuring using a 10:1 scope probe with say 13pF >tip capacitance. >The 'FSadjust' and 'Rset' can be used for AGC. Put a DC 'level set' voltage >on the Rser resistor end that normally connects to 0V. (OV=max out). Idea is >to throttle the output swing to (say) 1/2 of normal, which then allows a >+50% increase to compensate for losses. > Thanks John. I'll try playing around with that.
From: Joerg on 29 Nov 2009 17:00 Jim Thompson wrote: > On Sun, 29 Nov 2009 09:40:02 -0800, Joerg <invalid(a)invalid.invalid> > wrote: > >> Hammy wrote: >>> I have a signal between 100kHz to 10MHz sinusoidal DAC output. The >>> signal starts out at 650mVpp low frequency with a small DC offset of >>> about 10mV. As the frequency increases the DC offset increases and the >>> pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to >>> about 100mVpp with about 500mV DC offset. >>> >>> Are there any single chip or small parts count solution AGC that can >>> maintain a constant 650mVpp output under the above conditions. >>> >>> I've been goggling AGC and haven't had much luck other then 100 part >>> count schematics there must be an integrated version? >> >> Yes, but it's expensive: >> >> http://www.analog.com/static/imported-files/Data_Sheets/AD8367.pdf >> >> If on a budget you could build one around a uA733 or similar chip, add a >> simple detector and a FET as the gain control element. If your budget is >> super-tight use a dual-gate MOSFET which allows the gain control range >> you are looking for. One gate gets the signal, the other the control >> voltage. >> >> Here is another trick to save a buck: Characterize the signal drop >> versus frequency. Then use a simple gain control stage and place a 2nd >> DAC. This 2nd DAC is used to set the gain control input and is updated >> whenever you update the frequency. > > Years ago, I used a temperature-driven look-up table, controlling a > varicap, to make crystal oscillators as stable as oven-controlled... > without the power requirements of an oven. > You did WHAT? A LUT? Meaning digital stuff? <gasp> Now go, stand in the corner, and be ashamed. Tsk, tsk, tsk ... -- SCNR, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
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