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From: Jim Thompson on 29 Nov 2009 18:27
On Sun, 29 Nov 2009 14:00:01 -0800, Joerg <invalid(a)invalid.invalid>
wrote:

>Jim Thompson wrote:
>> On Sun, 29 Nov 2009 09:40:02 -0800, Joerg <invalid(a)invalid.invalid>
>> wrote:
>>
>>> Hammy wrote:
>>>> I have a signal between 100kHz to 10MHz sinusoidal DAC output. The
>>>> signal starts out at 650mVpp low frequency with a small DC offset of
>>>> about 10mV. As the frequency increases the DC offset increases and the
>>>> pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to
>>>> about 100mVpp with about 500mV DC offset.
>>>>
>>>> Are there any single chip or small parts count solution AGC that can
>>>> maintain a constant 650mVpp output under the above conditions.
>>>>
>>>> I've been goggling AGC and haven't had much luck other then 100 part
>>>> count schematics there must be an integrated version?
>>>
>>> Yes, but it's expensive:
>>>
>>> http://www.analog.com/static/imported-files/Data_Sheets/AD8367.pdf
>>>
>>> If on a budget you could build one around a uA733 or similar chip, add a
>>> simple detector and a FET as the gain control element. If your budget is
>>> super-tight use a dual-gate MOSFET which allows the gain control range
>>> you are looking for. One gate gets the signal, the other the control
>>> voltage.
>>>
>>> Here is another trick to save a buck: Characterize the signal drop
>>> versus frequency. Then use a simple gain control stage and place a 2nd
>>> DAC. This 2nd DAC is used to set the gain control input and is updated
>>> whenever you update the frequency.
>>
>> Years ago, I used a temperature-driven look-up table, controlling a
>> varicap, to make crystal oscillators as stable as oven-controlled...
>> without the power requirements of an oven.
>>
>
>You did WHAT? A LUT? Meaning digital stuff? <gasp>
>
>Now go, stand in the corner, and be ashamed. Tsk, tsk, tsk ...

The client, Saunders and Associates (builders of crystal testing
equipment) did the LUT. I did the analog and A/D/A interfaces.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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From: Joerg on 29 Nov 2009 19:13
Jim Thompson wrote:
> On Sun, 29 Nov 2009 14:00:01 -0800, Joerg <invalid(a)invalid.invalid>
> wrote:
>
>> Jim Thompson wrote:
>>> On Sun, 29 Nov 2009 09:40:02 -0800, Joerg <invalid(a)invalid.invalid>
>>> wrote:
>>>
>>>> Hammy wrote:
>>>>> I have a signal between 100kHz to 10MHz sinusoidal DAC output. The
>>>>> signal starts out at 650mVpp low frequency with a small DC offset of
>>>>> about 10mV. As the frequency increases the DC offset increases and the
>>>>> pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to
>>>>> about 100mVpp with about 500mV DC offset.
>>>>>
>>>>> Are there any single chip or small parts count solution AGC that can
>>>>> maintain a constant 650mVpp output under the above conditions.
>>>>>
>>>>> I've been goggling AGC and haven't had much luck other then 100 part
>>>>> count schematics there must be an integrated version?
>>>> Yes, but it's expensive:
>>>>
>>>> http://www.analog.com/static/imported-files/Data_Sheets/AD8367.pdf
>>>>
>>>> If on a budget you could build one around a uA733 or similar chip, add a
>>>> simple detector and a FET as the gain control element. If your budget is
>>>> super-tight use a dual-gate MOSFET which allows the gain control range
>>>> you are looking for. One gate gets the signal, the other the control
>>>> voltage.
>>>>
>>>> Here is another trick to save a buck: Characterize the signal drop
>>>> versus frequency. Then use a simple gain control stage and place a 2nd
>>>> DAC. This 2nd DAC is used to set the gain control input and is updated
>>>> whenever you update the frequency.
>>> Years ago, I used a temperature-driven look-up table, controlling a
>>> varicap, to make crystal oscillators as stable as oven-controlled...
>>> without the power requirements of an oven.
>>>
>> You did WHAT? A LUT? Meaning digital stuff? <gasp>
>>
>> Now go, stand in the corner, and be ashamed. Tsk, tsk, tsk ...
>
> The client, Saunders and Associates (builders of crystal testing
> equipment) did the LUT. I did the analog and A/D/A interfaces.
>

Good. Your are redeemed. Welcome back to the analog club :-)

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
From: Joerg on 29 Nov 2009 19:16
Hammy wrote:
> On Sun, 29 Nov 2009 09:40:02 -0800, Joerg <invalid(a)invalid.invalid>
> wrote:
>
>
>> Yes, but it's expensive:
>
> What isn't ;)
>
>> http://www.analog.com/static/imported-files/Data_Sheets/AD8367.pdf
>
> I was thinking of putting a digital pot in the AD8045 feedback loop.
> But by the time all is said and done 6 Bucks for the AD8637 looks
> pretty good.Newark sent me out a 25% off flyer so it's a good time to
> buy parts.
>

Careful with digital pots. They are essentially like flash drives. After
a certain amount of write cycles they could become unreliable. Just keep
that in mind when you are thinking about doing sweeps and stuff.

Hmm, 25% off, why don't they carry good beer?

[...]

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
From: JosephKK on 4 Dec 2009 15:57
On Sun, 29 Nov 2009 15:47:03 -0500, Hammy <spam(a)spam.com> wrote:

>On Sun, 29 Nov 2009 20:38:18 -0000, "john jardine"
><zen177928(a)zen.co.uk> wrote:
>
>>
>>"Hammy" <spam(a)spam.com> wrote in message
>>news:88v4h55c3d0fj1ilbfh6v41mjkqda0r3j2(a)4ax.com...
>>>I have a signal between 100kHz to 10MHz sinusoidal DAC output. The
>>> signal starts out at 650mVpp low frequency with a small DC offset of
>>> about 10mV. As the frequency increases the DC offset increases and the
>>> pk-pk voltage decreases. At 10 MHz my signal pk-pk has deteriorated to
>>> about 100mVpp with about 500mV DC offset.
>>>
>>> Are there any single chip or small parts count solution AGC that can
>>> maintain a constant 650mVpp output under the above conditions.
>>>
>>> I've been goggling AGC and haven't had much luck other then 100 part
>>> count schematics there must be an integrated version?
>>
>>With a 50MHz clock the signal would normally drop to maybe 500mV at 10MHz
>>but that's assuming you're measuring using a 10:1 scope probe with say 13pF
>>tip capacitance.
>>The 'FSadjust' and 'Rset' can be used for AGC. Put a DC 'level set' voltage
>>on the Rser resistor end that normally connects to 0V. (OV=max out). Idea is
>>to throttle the output swing to (say) 1/2 of normal, which then allows a
>>+50% increase to compensate for losses.
>>
>Thanks John.
>
>I'll try playing around with that.

With all that has been said, i suspect a miswire or some circuit
problem. Both the DSS and the first OPA should be up to the task
(without the stated aberrations). Though it could very well be a
layout issue as well. Since the DSS is current output are you using
an appropriate termination and coupling to the OPA?
From: Hammy on 4 Dec 2009 19:34
On Fri, 04 Dec 2009 12:57:44 -0800,
"JosephKK"<quiettechblue(a)yahoo.com> wrote:


>With all that has been said, i suspect a miswire or some circuit
>problem. Both the DSS and the first OPA should be up to the task
>(without the stated aberrations). Though it could very well be a
>layout issue as well. Since the DSS is current output are you using
>an appropriate termination and coupling to the OPA?


Actually I'm embarrassed to say I had my probe on 1x (I know stupid).
I really have to stop doing that it's getting ridiculous.

I'm just working on the power supply now.

On the plus side I learnt a lot about AGC ccts and what's out there
for future reference.

Thanks to all who helped.
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