Is an inout reg allowed
in [FPGA]
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From: Giorgos Tzampanakis on 4 Mar 2010 21:22 I've tried to use an inout reg with quartus and it doesn't give a warning. However, I read on the internet that an inout port can only be a wire. Which one is true?
From: Jonathan Bromley on 5 Mar 2010 03:28 On Fri, 5 Mar 2010 02:22:20 +0000 (UTC), Giorgos Tzampanakis wrote: >I've tried to use an inout reg with quartus and it doesn't give a >warning. However, I read on the internet that an inout port can >only be a wire. Which one is true? It is unquestionably true that an inout port must be a net (wire), and also that you must connect a net to any inout port when you instantiate the module. "reg" on either side of an inout port is definitely illegal. If your design uses the inout port in a unidirectional manner, it is possible that synthesis might be able to do something useful with a reg on one or other side of it. However, the resulting illegal Verilog code will never work in any simulator. Don't do it. The classic use of an inout port, to provide a bidi tri-state signal, is straightforward. Inside the module you need two signals or expressions - probably reg - to provide the buffer enable and buffer data. You then use a continuous assign to imply the buffer: module has_bidi ( inout bidi, ...); ... reg bidi_enable; reg bidi_drive_value; wire bidi_receive_value; ... assign bidi = bidi_enable? bidi_drive_value: 1'bx; assign bidi_receive_value = bidi; ... .... other logic to use "bidi_receive_value" .... and generate "bidi_enable" and "bidi_drive_value" endmodule The second "assign" does nothing more than renaming the port for internal use, but it can often be convenient to do that. -- Jonathan Bromley
From: Nathan Bialke on 5 Mar 2010 12:41 Hello, Out of curiousity, why does your tristate buffer model drive an x instead of a z? - Nathan On Mar 5, 12:28 am, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> wrote: > On Fri, 5 Mar 2010 02:22:20 +0000 (UTC), Giorgos Tzampanakis wrote: > >I've tried to use an inout reg with quartus and it doesn't give a > >warning. However, I read on the internet that an inout port can > >only be a wire. Which one is true? > > It is unquestionably true that an inout port must be a net > (wire), and also that you must connect a net to any inout > port when you instantiate the module. "reg" on either > side of an inout port is definitely illegal. > > If your design uses the inout port in a unidirectional > manner, it is possible that synthesis might be able to > do something useful with a reg on one or other side of it. > However, the resulting illegal Verilog code will never > work in any simulator. Don't do it. > > The classic use of an inout port, to provide a bidi > tri-state signal, is straightforward. Inside the module > you need two signals or expressions - probably reg - > to provide the buffer enable and buffer data. You then > use a continuous assign to imply the buffer: > > module has_bidi ( inout bidi, ...); > ... > reg bidi_enable; > reg bidi_drive_value; > wire bidi_receive_value; > ... > assign bidi = bidi_enable? bidi_drive_value: 1'bx; > assign bidi_receive_value = bidi; > ... > .... other logic to use "bidi_receive_value" > .... and generate "bidi_enable" and "bidi_drive_value" > endmodule > > The second "assign" does nothing more than renaming the port > for internal use, but it can often be convenient to do that. > -- > Jonathan Bromley
From: Jonathan Bromley on 5 Mar 2010 13:30 On Fri, 5 Mar 2010 09:41:25 -0800 (PST), Nathan Bialke wrote: >Out of curiousity, why does your tristate buffer model drive an x >instead of a z? ah, good catch. Runs for cover with tail between legs. Of course you're right, it should have been � assign bidi = bidi_enable? bidi_drive_value: 1'bz; Errrrm, that's what simulators are for, right? To catch the idiotic typing mistakes? Thanks! -- Jonathan Bromley
From: Anssi Saari on 5 Mar 2010 13:36
Nathan Bialke <nathan(a)bialke.com> writes: > Hello, > > Out of curiousity, why does your tristate buffer model drive an x > instead of a z? In my experience this is a fairly common technique to make sure some other part of the design isn't erroneously reading the x values and passing them on. |