Itanium had appeal
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From: MitchAlsup on 27 Apr 2010 18:16 On Apr 27, 2:22 pm, n...(a)cam.ac.uk wrote: > In article <cf25e322-30f4-4915-947d-aebdbe28e...(a)d12g2000vbr.googlegroups..com>, > Yes, that's true - for CPU architectures - but I was also thinking > of programming languages! I was also thinking about other aspects, programming languages included. Mitch
From: MitchAlsup on 27 Apr 2010 18:24 On Apr 27, 2:13 pm, Robert Myers <rbmyers...(a)gmail.com> wrote: > There > were no cubic dollars at the beginning of the attack of the killer > micros, and right up until it nearly went out of business, IBM was > certain that its business model could not be defeated. There were a few (albeit small) cubic dollars, mainly driven by companies trying to establish themselves in the new world of computer on a chip (ala 6809-ish levels) for their own goals. In general the dollars were small enough that the companies could "take a chance" and allow some engineers to "go do it" and if it failed, hide the research in the pit of no return. Certainly there was no integrated Wintel bringing, CPUs, chips, motherboards, operating systems and software as one big consumer friendly package. Crushing everyone who even attempts to stand on the garden of Wintelidom. {Agreed about the IBM business model up until they almost bought the farm.} Mitch
From: Chris Gray on 27 Apr 2010 18:46 Quadibloc <jsavard(a)ecn.ab.ca> writes: > I would indeed think that the idea of an "interrupt-free architecture" > would scare people. What, do all the I/O with wait loops? I'm surprised no-one has mentioned it on this thread yet, but the Tera MTA chips had neither interrupts nor page faults. They implemented a BSD-like system on top of that. I/O was done by polling - they could afford a thread doing that because they had 128 available per chip. Lack of page faults required that they go back to full-program swapping for multi-tasking. -- Chris Gray cg(a)GraySage.COM
From: Terje Mathisen "terje.mathisen at on 27 Apr 2010 19:19 MitchAlsup wrote: > On Apr 27, 4:36 pm, Terje Mathisen<"terje.mathisen at tmsw.no"> > wrote: >> Anton Ertl wrote: >>> Terje Mathisen<"terje.mathisen at tmsw.no"> writes: >>>> The ALAT is similar to LLSC in that it will detect all modifications, >>>> including a rewrite of the same value. >> >>> I don't think that the ALAT does any better. It will notice that >>> something was stored at the loaded address, but it won't notice if >>> somebody changed something that dependent loads accessed, so the >>> program will have to check them with the ALAT in all situations where >>> they will have to do it with the double-loading approach. >> >> No, the critical difference is the ability to detect all writes to >> protected locations, including rewrites of the same value: >> >> This means that any app which blindly writes the entire chain when >> updating would only need to check the start of the chain. > > With respect to the ABA problem and synchronization, a rewrite of a > critical location even with the same resulting bit pattern is still an > event that must terminate a synchronization attempt. At the very Exactly what I was trying to say, thanks.:-) Terje > minimum, it is exceedingly dangerous to allow a synchronize to assume > that it is successful when some other party has write-touched one of > its critical storage locations. This was THE situation where the ABA > problem acquired its name. > > With respect to other programming model uses outside of > synchronization, I don't know. > > Mitch -- - <Terje.Mathisen at tmsw.no> "almost all programming can be viewed as an exercise in caching"
From: nmm1 on 28 Apr 2010 03:39
In article <87pr1kzf79.fsf(a)ami-cg.GraySage.com>, Chris Gray <cg(a)graysage.com> wrote: >Quadibloc <jsavard(a)ecn.ab.ca> writes: > >> I would indeed think that the idea of an "interrupt-free architecture" >> would scare people. What, do all the I/O with wait loops? > >I'm surprised no-one has mentioned it on this thread yet, but the Tera MTA >chips had neither interrupts nor page faults. They implemented a BSD-like >system on top of that. I/O was done by polling - they could afford a thread >doing that because they had 128 available per chip. Lack of page faults >required that they go back to full-program swapping for multi-tasking. I knew that they never interrupted applications, but not that they were completely interrupt-free. Interesting. I never claimed that what I was proposing was original - merely radical, and the Tera MTA was that :-) Actually, on modern systems, you very rarely need to do much swapping, because you usually have enough memory to keep all active programs in memory simultaneously. You can get much better disk efficiencies by swapping rather than paging, anyway. Regards, Nick Maclaren. |