Itanium had appeal
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From: Joe Pfeiffer on 29 Apr 2010 18:26 Rick Jones <rick.jones2(a)hp.com> writes: > nmm1(a)cam.ac.uk wrote: >> In article <hrci7n$hak$2(a)usenet01.boi.hp.com>, >> Rick Jones <rick.jones2(a)hp.com> wrote: >> >What implications would polling have for power consumption? >> >Keeping a thread (or threads probably) going lickety-split checking >> >for I/O completions without unpleasant latency would tend to >> >preclude getting into a nice low-power state wouldn't it? > >> Not if done competently. A simple primitive that says "put me to >> sleep until event X happens" is what is needed. > > What would event X be then if not an interrupt or its functional > equivalent? Depends on how broadly you take "functional equivalent". I wouldn't regard "stall this core's clock until a change occurs in that input register" to be functionally equivalent to an interrupt; others might. -- As we enjoy great advantages from the inventions of others, we should be glad of an opportunity to serve others by any invention of ours; and this we should do freely and generously. (Benjamin Franklin)
From: Joe Pfeiffer on 29 Apr 2010 18:32 A current machine with no interrupts is the Parallax Propeller -- it uses eight simple cores, and is intended for embedded applications, The idea is to move as much IO handling as possible off of peripherals like UARTs, and do it all with polling and bit-banging. -- As we enjoy great advantages from the inventions of others, we should be glad of an opportunity to serve others by any invention of ours; and this we should do freely and generously. (Benjamin Franklin)
From: Morten Reistad on 30 Apr 2010 01:26
In article <hrcv4s$nm8$2(a)usenet01.boi.hp.com>, Rick Jones <rick.jones2(a)hp.com> wrote: >nmm1(a)cam.ac.uk wrote: >> In article <hrci7n$hak$2(a)usenet01.boi.hp.com>, >> Rick Jones <rick.jones2(a)hp.com> wrote: >> >What implications would polling have for power consumption? >> >Keeping a thread (or threads probably) going lickety-split checking >> >for I/O completions without unpleasant latency would tend to >> >preclude getting into a nice low-power state wouldn't it? > >> Not if done competently. A simple primitive that says "put me to >> sleep until event X happens" is what is needed. > >What would event X be then if not an interrupt or its functional >equivalent? This could be a (hardware-layer) blocking read on a fifo. Redesigning I/O to use fifo's similar to hyperchannels should not be too hard if you are Intel or AMD. Then you just have one or more processors go read from that fifo, and block. You then handle I/O with message passing. And then make fifo-to-pci, fifo-to-usb, fifo-to-sata bridges. Suddenly, no interrupts. We could have a fifo-to-mmu as well, and do paging with no interrupts. -- mrr |