LVDS i/o in a SystemVerilog Interface block
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From: fpgabuilder on 1 Mar 2010 20:28 I need to instantiate LVDS interfaces in my top-level. I am planning to use SV interface blocks. Altera's documentation suggests that LVDS i/os should only be instantiated using a megafunction. But the interface blocks do not allow hierarchy so I cannot instantiate a megafunction inside the interface block. Any thoughts on this?
From: Jonathan Bromley on 2 Mar 2010 04:39 On Mon, 1 Mar 2010 17:28:38 -0800 (PST), fpgabuilder wrote: >I need to instantiate LVDS interfaces in my top-level. I am planning >to use SV interface blocks. Altera's documentation suggests that LVDS >i/os should only be instantiated using a megafunction. But the >interface blocks do not allow hierarchy so I cannot instantiate a >megafunction inside the interface block. > >Any thoughts on this? This sounds to me like an inappropriate use of SV interfaces. When you say "I am planning to use SV interface blocks", what exactly do you intend? Interfaces are useful in certain situations, but you definitely would not want to use them everywhere in your design. In particular, you should avoid using interfaces for the design's top-level I/O because it will inevitably cause trouble with other tools in the flow. It is not quite true that "interfaces do not allow hierarchy". You cannot create a *module* instance inside an interface, but you certainly can have an *interface* instance inside another. However, nested interface instances are not necessarily synthesizable. -- Jonathan Bromley
From: fpgabuilder on 2 Mar 2010 11:53
On Mar 2, 1:39 am, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> wrote: > On Mon, 1 Mar 2010 17:28:38 -0800 (PST), fpgabuilder wrote: > >I need to instantiate LVDS interfaces in my top-level. I am planning > >to use SV interface blocks. Altera's documentation suggests that LVDS > >i/os should only be instantiated using a megafunction. But the > >interface blocks do not allow hierarchy so I cannot instantiate a > >megafunction inside the interface block. > > >Any thoughts on this? > > This sounds to me like an inappropriate use of SV interfaces. > When you say "I am planning to use SV interface blocks", what > exactly do you intend? Interfaces are useful in certain > situations, but you definitely would not want to use them > everywhere in your design. In particular, you should avoid > using interfaces for the design's top-level I/O because it > will inevitably cause trouble with other tools in the flow. > > It is not quite true that "interfaces do not allow hierarchy". > You cannot create a *module* instance inside an interface, > but you certainly can have an *interface* instance inside > another. However, nested interface instances are not > necessarily synthesizable. > -- > Jonathan Bromley Interesting. That is exactly what I was intending to do i.e. use interfaces in my top-level i/os. What kind of tool issues you think this will cause? I am still new to interfaces and system verilog in general and was going through Sutherland, et. all's book SystemVerilog for Design. We only use two tools in our environment... Quartus and Modelsim DE. Quartus's documentation says it supports interfaces... not sure if it supports hierarchy but I was going to try that as well. In our environment where we do not have separate verification and design teams most of the engineers prefer reuse across synthesizable code and verification test benches. Therefore, it seems like use of interfaces in top-level i/o is a good idea albeit if the tool supports it which brings back to the point you raised. |