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From: Steve Pope on 4 Apr 2010 02:45
Jerry Avins <jya(a)ieee.org> wrote:

>Asynchronous operation is commom in hardware FIFOs. I may have built the
>first with discrete IC logic, and I recall a few LSI designs. Chuck
>Moore of Forth fame builds CPUs that way.

Async operation is also common in all modern DRAM's. In fact
I would say that the current prevalent ASIC timing model, which
is timing closure, is an asynchronous approach, when compared
with earlier disciplines such as IBM's LSSD's or Mead-Conway
non-overlapping clocks. These earlier approaches tried to make
an entire chip, or at least more of a chip, synchronous. This
is now no longer done.

So in a sense, the systolic asynchronous array approach won the
architecture battle. It's just not done explicitly at an architecture
level; it's implemented in the backend.

Note to all: I tried to wedge things such that I could go to
Kansas City, but it failed, so I won't be there. I wish I could,
and I thank all the organizers and contributors. Have a grand time.


S.
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