Lookup Table Vs. FIR For Modulator Pulse Shaping
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From: Randy Yates on 27 Mar 2010 21:36 Hi People, I'm trying to think of an efficient way to implement a Shaped OQPSK modulator in hardware (FPGA or CPLD). My first thought was to use an FIR filter. However, since there are only two input bits per symbol, there are only a relatively small number of output states and (it seems) a LUT could be much more efficient. Has anyone thought through this a little better and have any pointers or suggestions? -- Randy Yates % "And all you had to say Digital Signal Labs % was that you were mailto://yates(a)ieee.org % gonna stay." http://www.digitalsignallabs.com % Getting To The Point', *Balance of Power*, ELO
From: Eric Jacobsen on 27 Mar 2010 22:17 On 3/27/2010 6:36 PM, Randy Yates wrote: > Hi People, > > I'm trying to think of an efficient way to implement a Shaped OQPSK > modulator in hardware (FPGA or CPLD). My first thought was to use an FIR > filter. However, since there are only two input bits per symbol, there > are only a relatively small number of output states and (it seems) a LUT > could be much more efficient. > > Has anyone thought through this a little better and have any pointers > or suggestions? A lut is a very common way to implement a modulator. You only need enough address bits to cover N symbols plus however many phases you want per symbol (four is often enough). You can even add address bits for different pulse shapes or modulation orders. Even in an FPGA, if the symbol rate is fixed, this is often the most efficient way to do it. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: glen herrmannsfeldt on 28 Mar 2010 01:28 Randy Yates <yates(a)ieee.org> wrote: > I'm trying to think of an efficient way to implement a Shaped OQPSK > modulator in hardware (FPGA or CPLD). My first thought was to use an FIR > filter. However, since there are only two input bits per symbol, there > are only a relatively small number of output states and (it seems) a LUT > could be much more efficient. Well, the primary logic unit of an FPGA is look-up table. If you are multiplying by constants, especially with a two bit input, yes, look-up tables are likely the best way. It is usual for FPGAs to have flip-flops at the output of each LUT, which makes systolic array pipelines real easy to build. If you latch at each logic level, they are really fast, too! Not knowing OQPSK, can you describe a little what expression you need evaluated? -- glen
From: Vladimir Vassilevsky on 28 Mar 2010 07:59 Randy Yates wrote: > Hi People, > > I'm trying to think of an efficient way to implement a Shaped OQPSK > modulator in hardware (FPGA or CPLD). My first thought was to use an FIR > filter. However, since there are only two input bits per symbol, there > are only a relatively small number of output states and (it seems) a LUT > could be much more efficient. > > Has anyone thought through this a little better and have any pointers > or suggestions? Using LUT for modulators is pretty common; see G3RUH GMSK modem for example. However, FPGA utilization is going to be rather inefficient if you need LUT for more then, say, 256 entries. I cheer those who work on weekends. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
From: Greg Berchin on 28 Mar 2010 08:09
On Sun, 28 Mar 2010 06:59:26 -0500, Vladimir Vassilevsky <nospam(a)nowhere.com> wrote: >I cheer those who work on weekends. What's a weekend? Greg |