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From: Steve at fivetrees on 16 Dec 2009 17:45
"Vladimir Vassilevsky" <nospam(a)nowhere.com> wrote in message
news:UoednXBfd-N5drXWnZ2dnUVZ_h-dnZ2d(a)giganews.com...
>
> Steve at fivetrees wrote:
>
>> Heh. I actually just asked for any other data on the MAX11043, such as
>> application notes... I was told there is no other data.
>
> MAXIM has well deceived bad reputation for parts availability; are you
> planning to check it on your own?

Heh again. Distributors here in the UK (e.g. Farnell) have (and have had)
reasonable stock, otherwise I wouldn't touch it with a bargepole.

It happens that this device suits us exceedingly well, and boy, have we
researched this...

> For 4-channel sampling at ~200kHz for streaming over the Ethernet, the low
> cost solution would be 192kHz audio ADC.

Excellent point, except for the fact that one reason we got into this
project was to get away from a certain TI family of 192kHz audio ADCs, which
have a noise-shaping issue (so I'm told) which my boss is keen to leave
behind... And said boss has told us to lose the self-same 192kHz audio ADCs,
which we'd included as another option, from our prototype. (Said prototype
also exists to prove a bunch of other technologies, all equally fraught, and
is really intended to allow us to validate them all.)

There are times when I wish I were a monk. Today has been one of those days.

Steve
--
http://www.fivetrees.com


From: Tom on 16 Dec 2009 20:13
In article <-eGdnbKi0oh5ObXWnZ2dnUVZ8hOdnZ2d(a)pipex.net>, "Steve at fivetrees" <steve(a)NOSPAMTAfivetrees.com> wrote:
>Maybe I wasn't clear enough - the problem is that, while the CPU can do SPI
>under DMA control, the DMA sequence is initiated in software. I can see no
>way at all of starting an SPI DMA sequence in hardware, which was my
>original expectation.

I understand that there is no way to hardware-trigger the DMA in SPI master
mode but what if you configure the SPI for slave mode and then start the DMA?
Will the DMA wait until some external source (like a counter) starts
generating CLK pulses and shifting the data from the ADC to the CPU? If it
will, then all you need to add is a counter that is triggered by EOC and
generates 64 CLK pulses before waiting for another EOC.
From: langwadt on 16 Dec 2009 20:39
On 16 Dec., 00:41, "Steve at fivetrees" <st...(a)NOSPAMTAfivetrees.com>
wrote:
> I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
> output). It has an end-of-conversion pin, which when active means that a
> bunch of data is available to read via SPI.
>
> Which is fine, except I want to run this baby at 200kHz (ish). Which means
> that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
> AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages - not
> one sample at a time ;) - so needs to be aggregated into main memory for
> despatch (with some extra room for Ethernet delays, say 1s-worth). The CPU
> does have a SPI DMA subsystem, but needs to be primed in code...
>
> So - one way of solving this is to find (or design) a FIFO with SPI in, and
> SPI (or any other form of DMA-able CPU subsystem - again seems nuts to
> shuffle this one byte at a time) out. Short of a Lattice IP core, I'm
> finding nothing off-the-shelf. Could design some logic to use a parallel
> dual-port FIFO, but seems wrong: I'd have to convert from SPI to parallel on
> the way in, and the reverse on the way out.
>
> I've asked Maxim the obvious question: how do I interface to this thing?
> They've not been able to help.
>
> Any ideas, folks?
>
> Steve
> --http://www.fivetrees.com

would a 200KHz interrupt really be that bad?, write it in assembler if
needed,
can't be that many instructions if all it needs to do is copy a few
bytes and return.
I'd rather use 5-10% of the cpu on an interrupt than try to try and
kludge together
fifos and a bunch of logic and hope it works.



-Lasse
From: Steve at fivetrees on 17 Dec 2009 16:15
"Tom" <tom(a)nospam.com> wrote in message
news:DAfWm.107031$gg6.61273(a)newsfe25.iad...
> In article <-eGdnbKi0oh5ObXWnZ2dnUVZ8hOdnZ2d(a)pipex.net>, "Steve at
> fivetrees" <steve(a)NOSPAMTAfivetrees.com> wrote:
>>Maybe I wasn't clear enough - the problem is that, while the CPU can do
>>SPI
>>under DMA control, the DMA sequence is initiated in software. I can see no
>>way at all of starting an SPI DMA sequence in hardware, which was my
>>original expectation.
>
> I understand that there is no way to hardware-trigger the DMA in SPI
> master
> mode but what if you configure the SPI for slave mode and then start the
> DMA?
> Will the DMA wait until some external source (like a counter) starts
> generating CLK pulses and shifting the data from the ADC to the CPU? If it
> will, then all you need to add is a counter that is triggered by EOC and
> generates 64 CLK pulses before waiting for another EOC.

You, sir, are a blinking hero. That idea not only has legs, it works out
even better than that. The EOC signal goes false when all bits are shifted
out, so there's no need for a counter. Basically, this method adds the
capability to be an SPI master to the MAX11043, which was the simplifying
insight we were lacking (and which we've spent the afternoon kicking
ourselves about). It's really quite beautiful.

There's one little remaining bit of kludginess - while the MAX11043 has data
in, data out (and clock in), the AVR has MOSI and MISO (and clock in/out).
MISO and MOSI reverse directions when changing from master to slave, but
that's ok, I can deal with that in hardware (driven by a pair of GPIO pins).
We do need to talk to the MAX11043 too, to configure it...

We still need to prove that a 16-bit DMA transfer is complete before the
next 16 bits are shifted in (the max the AVR can handle in one chunk), but
we're working on that.

Thanks, Tom, I owe you a pint.

Steve
--
http://www.fivetrees.com


From: Steve at fivetrees on 17 Dec 2009 16:17
<langwadt(a)fonz.dk> wrote in message
news:69d93693-d2df-43af-9d28-b04b4235f8cb(a)c3g2000yqd.googlegroups.com...
>
> would a 200KHz interrupt really be that bad?, write it in assembler if
> needed,
> can't be that many instructions if all it needs to do is copy a few
> bytes and return.
> I'd rather use 5-10% of the cpu on an interrupt than try to try and
> kludge together
> fifos and a bunch of logic and hope it works.

One of my colleagues has already tested this idea, by injecting a 200kHz
signal into an IRQ pin. He tells me there's time for the ISR to be called
and to return, and almost nothing else. Certainly not time enough to do
anything useful.

I've not double-checked his work ;).

Steve
--
http://www.fivetrees.com


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