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From: Steve at fivetrees on 15 Dec 2009 18:41
I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
output). It has an end-of-conversion pin, which when active means that a
bunch of data is available to read via SPI.

Which is fine, except I want to run this baby at 200kHz (ish). Which means
that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages - not
one sample at a time ;) - so needs to be aggregated into main memory for
despatch (with some extra room for Ethernet delays, say 1s-worth). The CPU
does have a SPI DMA subsystem, but needs to be primed in code...

So - one way of solving this is to find (or design) a FIFO with SPI in, and
SPI (or any other form of DMA-able CPU subsystem - again seems nuts to
shuffle this one byte at a time) out. Short of a Lattice IP core, I'm
finding nothing off-the-shelf. Could design some logic to use a parallel
dual-port FIFO, but seems wrong: I'd have to convert from SPI to parallel on
the way in, and the reverse on the way out.

I've asked Maxim the obvious question: how do I interface to this thing?
They've not been able to help.

Any ideas, folks?

Steve
--
http://www.fivetrees.com


From: Jon Kirwan on 15 Dec 2009 19:38
On Tue, 15 Dec 2009 23:41:53 -0000, "Steve at fivetrees"
<steve(a)NOSPAMTAfivetrees.com> wrote:

>I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
>output). It has an end-of-conversion pin, which when active means that a
>bunch of data is available to read via SPI.
>
>Which is fine, except I want to run this baby at 200kHz (ish). Which means
>that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
>AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages - not
>one sample at a time ;) - so needs to be aggregated into main memory for
>despatch (with some extra room for Ethernet delays, say 1s-worth). The CPU
>does have a SPI DMA subsystem, but needs to be primed in code...
>
>So - one way of solving this is to find (or design) a FIFO with SPI in, and
>SPI (or any other form of DMA-able CPU subsystem - again seems nuts to
>shuffle this one byte at a time) out. Short of a Lattice IP core, I'm
>finding nothing off-the-shelf. Could design some logic to use a parallel
>dual-port FIFO, but seems wrong: I'd have to convert from SPI to parallel on
>the way in, and the reverse on the way out.
>
>I've asked Maxim the obvious question: how do I interface to this thing?
>They've not been able to help.
>
>Any ideas, folks?

A hardware FIFO was the first thing that crossed my mind. But I think
you've excluded it. (You might use a dedicated mcu for the FIFO with
custom, slightly wider than 1-bit serial shifting if you wanted?)

I'm using a SiLabs C8051F061, right now, running its 16 bit SAR ADC at
more than 500kHz and having no problems with it. But it includes a
DMA unit inside, so things just lope along fine. Data is taken in
bursts lasting a few milliseconds so it's easy on the micro interrupt
system.

In another system, I used an ADSP-21xx to operate a 16-bit ADC at
600ns per sample, driving the control lines entirely in software and
storing data on the fly. But it has 25ns cycle time and can pack a
memory read, memory write, and alu operation in a single cycle.

No outbound ethernet for streaming the data out in either case,
though.

Have you considered the thought that someone matched up the wrong
parts for the application?

Jon
From: Vladimir Vassilevsky on 15 Dec 2009 20:42


Steve at fivetrees wrote:

> I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
> output). It has an end-of-conversion pin, which when active means that a
> bunch of data is available to read via SPI.
>
> Which is fine, except I want to run this baby at 200kHz (ish). Which means
> that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
> AT32UC3A.)

Why 200kHz interrupt would be nuts? Handling one high priority interrupt
at 200kHz shouldn't be a problem for AVR32.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
From: Paul Carpenter on 15 Dec 2009 20:28
In article <OZGdnW0K7fNcg7XWnZ2dnUVZ8t6dnZ2d(a)pipex.net>,
steve(a)NOSPAMTAfivetrees.com says...
> I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
> output). It has an end-of-conversion pin, which when active means that a
> bunch of data is available to read via SPI.
>
> Which is fine, except I want to run this baby at 200kHz (ish). Which means
> that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
> AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages - not
> one sample at a time ;) - so needs to be aggregated into main memory for
> despatch (with some extra room for Ethernet delays, say 1s-worth). The CPU
> does have a SPI DMA subsystem, but needs to be primed in code...

So why not do the code for SPI with DMA?

If you are sending data in Ethernet packets, you will be buffering the
data to build up your packet size, so what is the problem with filling
buffers using DMA?

Yes I can see it is a complicated device to setup, but I do not see what
the issue with getting code to run on simple proving of getting four
simulutaneous samples using SPI DMA. Using a GPIO to drive CONVRUN
and EOC to trigger DMA subsystem.

Is there an issue getting the clock and data phasing right to match the
devices for SPI?

> So - one way of solving this is to find (or design) a FIFO with SPI in, and
> SPI (or any other form of DMA-able CPU subsystem - again seems nuts to
> shuffle this one byte at a time) out. Short of a Lattice IP core, I'm
> finding nothing off-the-shelf. Could design some logic to use a parallel
> dual-port FIFO, but seems wrong: I'd have to convert from SPI to parallel on
> the way in, and the reverse on the way out.

Sounds like a sledgehammer to crack a nut, if you were going to
externally FIFO with some sort of PLD/FPGA, then I would consider
DMAing the parallel data.

> I've asked Maxim the obvious question: how do I interface to this thing?
> They've not been able to help.

It may be they did not understand your question.

> Any ideas, folks?
>
> Steve
>

--
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<http://www.pcserviceselectronics.co.uk/> PC Services
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From: Tom on 15 Dec 2009 21:51
In article <OZGdnW0K7fNcg7XWnZ2dnUVZ8t6dnZ2d(a)pipex.net>, "Steve at fivetrees" <steve(a)NOSPAMTAfivetrees.com> wrote:
>I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
>output). It has an end-of-conversion pin, which when active means that a
>bunch of data is available to read via SPI.
>
>Which is fine, except I want to run this baby at 200kHz (ish). Which means
>that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
>AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages - not
>one sample at a time ;) - so needs to be aggregated into main memory for
>despatch (with some extra room for Ethernet delays, say 1s-worth). The CPU
>does have a SPI DMA subsystem, but needs to be primed in code...

I've never used an AT32UC3A but is there any way to use an external I/O pin to
pause the DMA? If not, then how about running the SPI in slave mode with the
clock coming from an external source that is triggered by the EOC pin? This
would effectively match the DMA speed with the conversion rate of your ADC.

I just did a quick look at the datasheet to see if I couldn't figure this out
myself but I'm lost... the description of the PSR in the DMA controller in
section 21.5.4 (page 159 of 826) says "See the part specific documentation for
details". Huh?

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