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From: RCIngham on 25 May 2010 09:07
[snip]
>
>Thanks for your info, but I have to generate this signals in a new vhdl
>module

Yes.

>or in the top level module??
>
>Jose
>

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From: Eagle_mk4 on 27 May 2010 12:00
And someone can help me with an example for write a random data into any
address, I mean an example of how should be the module with the input
signals.

Thanks.

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From: Brian Drummond on 27 May 2010 16:39
On Thu, 27 May 2010 11:00:30 -0500, "Eagle_mk4"
<eagle_mk4(a)n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:

>And someone can help me with an example for write a random data into any
>address, I mean an example of how should be the module with the input
>signals.

There should be one in the files you generated with Coregen when you
created the MIG design

- Brian
From: Eagle_mk4 on 31 May 2010 05:34
>On Thu, 27 May 2010 11:00:30 -0500, "Eagle_mk4"
><eagle_mk4(a)n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:
>
>>And someone can help me with an example for write a random data into any
>>address, I mean an example of how should be the module with the input
>>signals.
>
>There should be one in the files you generated with Coregen when you
>created the MIG design
>
>- Brian
>

The testbench of example folder??

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