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From: John_H on 28 Mar 2010 17:18
On Mar 28, 8:31 am, Randy Yates <ya...(a)ieee.org> wrote:
> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
> that already has a high (baseband) sample rate - around 40-80 MHz.
>
> What kind of (single-bit) output rate can you get with a CPLD or FPGA
> device?

FPGAs are not analog devices!! You would probably want to have
something retime and buffer any delta-sigma style signal coming from
the FPGA to get the precision phase and amplitudes for a proper analog
result. Running clean analog cleanup filters at that frequency can be
pretty daunting as well. You could probably extend the lookup concept
for the raw delta sigma output stream but do you have the number of
needed bits figured out? For the analog case, you could add multiple
simple lookup values for multiple adjacent pulses to account for the
transmit intersymbol interference, no memory required. But for a
delta-sigma stream you need to have all the lookup bits to produce
your oversampled stream.

Your best bet for output rate would probably be LVDS differential. On
the Spartan-3A, for instance, you should be able to hit 668Mb/s. If
you go to the more costly families the Gigabit transceivers can go a
little beyond 3Gb/s.

Have you used delta-sigma converters before? Do you know what order
filter you'd be pursuing and what your oversampling rate needs to be
to achieve the 14 bits you were talking about? Or are you happy with
6 bits of I/Q effective resolution?

I don't know of anyone personally who has rolled their own delta sigma
DACs but I know there are different kinds out there including a
bandpass style that gives modulation of a carrier, typically Fs/4,
that could help you achieve your end result cleaner. You could
conceivably go straight mixer instead of I/Q modulator if you used the
lookup approach with a much wider lookup. Rather than using small on-
board memories, going much larger with an external SRAM or the jumbo
memory blocks like in the Altera Stratix parts could give you a direct
Delta Sigma stream output. The streams would have to be carefully
tailored to be spliceable or include some of the residual values from
the modulator making the lookup a huge table. At least I imagine
bandpass SAW filters are easier to come by in your frequency range.

Simplifying the project hardware sounds potentially fun but full of
opportunities to do things wrong.

Are you aware of the Analog Devices digital modulator chips? I used
to follow their TXDACs and saw them becoming more and more capable
over time.
From: Michael S on 28 Mar 2010 18:28
On Mar 28, 9:27 pm, Symon <symon_bre...(a)hotmail.com> wrote:
> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...(a)ieee.org> wrote:
> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
> >> that already has a high (baseband) sample rate - around 40-80 MHz.
>
> > That's a very bad idea.
> > For your sort of application homemade delta-sigma DAC can't match
> > combination of price, SNR, SFDR and power provided by something like
> > AD9754.
>
> I'm pretty sure on price and power (I assume efficiency?) his solution
> does match your suggested alternative given that, from details in his
> previous postings on this newsgroup, the FPGA/CPLD device is a sunk
> cost. I agree with your other acronyms though!
> Cheers, Syms.

At what rate do you have to generate pulses to build, say 12-bit 80
MSPS? I don't know the exact answer but pretty sure that the required
rate is way above capabilities of CPLDs and likely above what's
possible with smallest FPGAs.
You would need FPGA with the serializer implemented in hardware So,
still on the digital side, you are pushed from something like $4 up to
something like $30 or more. The difference already pays for several
AD9754s both in money and in power consumption. Now, consider all the
analog parts that you need to filter you pulse train into nice analog
signal. Since, even with mid-range FPGA you will have relatively
modest oversampling (factor of 15 or something like that) the analog
filter will have to be rather sharp and probably high order. It would
cost you more money and more power.

As I said above, implementing high speed DAC in programmable logic
device is very bad idea.
Implementing voice-grade (voice, not audio) DAC sounds less crazy but
from point of view of economics, power and board real estate even that
is more often than not a losing proposition.
From: Randy Yates on 28 Mar 2010 20:33
Michael S <already5chosen(a)yahoo.com> writes:

> On Mar 28, 9:27 pm, Symon <symon_bre...(a)hotmail.com> wrote:
>> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...(a)ieee.org> wrote:
>> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
>> >> that already has a high (baseband) sample rate - around 40-80 MHz.
>>
>> > That's a very bad idea.
>> > For your sort of application homemade delta-sigma DAC can't match
>> > combination of price, SNR, SFDR and power provided by something like
>> > AD9754.
>>
>> I'm pretty sure on price and power (I assume efficiency?) his solution
>> does match your suggested alternative given that, from details in his
>> previous postings on this newsgroup, the FPGA/CPLD device is a sunk
>> cost. I agree with your other acronyms though!
>> Cheers, Syms.
>
> At what rate do you have to generate pulses to build, say 12-bit 80
> MSPS? I don't know the exact answer but pretty sure that the required
> rate is way above capabilities of CPLDs and likely above what's
> possible with smallest FPGAs.
> You would need FPGA with the serializer implemented in hardware So,
> still on the digital side, you are pushed from something like $4 up to
> something like $30 or more. The difference already pays for several
> AD9754s both in money and in power consumption. Now, consider all the
> analog parts that you need to filter you pulse train into nice analog
> signal. Since, even with mid-range FPGA you will have relatively
> modest oversampling (factor of 15 or something like that) the analog
> filter will have to be rather sharp and probably high order. It would
> cost you more money and more power.
>
> As I said above, implementing high speed DAC in programmable logic
> device is very bad idea.
> Implementing voice-grade (voice, not audio) DAC sounds less crazy but
> from point of view of economics, power and board real estate even that
> is more often than not a losing proposition.

Michael,

"Bad" is relative to your criteria. Hint: in my application, cost and
power are not important. Size is very important. The AD9754 is 700 mils
long, not a small part, and you'd need two of them.

But I do agree it is not a good idea unless you really need it.

By the way, I have designed a production-quality delta sigma D/A. It
went in over 17M Sony Ericsson phones. But it was implemented in
software on a TMS320C54x, not FPGA. You can see a presentation I
made on it at the first comp.dsp conference here:

http://www.digitalsignallabs.com/presentation.pdf
--
Randy Yates % "I met someone who looks alot like you,
Digital Signal Labs % she does the things you do,
mailto://yates(a)ieee.org % but she is an IBM."
http://www.digitalsignallabs.com % 'Yours Truly, 2095', *Time*, ELO
From: John_H on 29 Mar 2010 00:24
On Mar 28, 8:33 pm, Randy Yates <ya...(a)ieee.org> wrote:
> Michael S <already5cho...(a)yahoo.com> writes:
> > On Mar 28, 9:27 pm, Symon <symon_bre...(a)hotmail.com> wrote:
> >> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...(a)ieee.org>  wrote:
> >> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
> >> >> that already has a high (baseband) sample rate - around 40-80 MHz.
>
> >> > That's a very bad idea.
> >> > For your sort of application homemade delta-sigma DAC can't match
> >> > combination of price, SNR, SFDR and power  provided by something like
> >> > AD9754.
>
> >> I'm pretty sure on price and power (I assume efficiency?) his solution
> >> does match your suggested alternative given that, from details in his
> >> previous postings on this newsgroup, the FPGA/CPLD device is a sunk
> >> cost. I agree with your other acronyms though!
> >> Cheers, Syms.
>
> > At what rate do you have to generate pulses to build, say 12-bit 80
> > MSPS? I don't know the exact answer but pretty sure that the required
> > rate is way above capabilities of CPLDs and likely above what's
> > possible with smallest FPGAs.
> > You would need FPGA with the serializer implemented in hardware So,
> > still on the digital side, you are pushed from something like $4 up to
> > something like $30 or more. The difference already pays for several
> > AD9754s both in money and in power consumption. Now, consider all the
> > analog parts that you need to filter you pulse train into nice analog
> > signal. Since, even with mid-range FPGA you will have relatively
> > modest oversampling (factor of 15 or something like that) the analog
> > filter will have to be rather sharp and probably high order. It would
> > cost you more money and more power.
>
> > As I said above, implementing high speed DAC in programmable logic
> > device is very bad idea.
> > Implementing voice-grade (voice, not audio) DAC sounds less crazy but
> > from point of view of economics, power and board real estate even that
> > is more often than not a losing proposition.
>
> Michael,
>
> "Bad" is relative to your criteria. Hint: in my application, cost and
> power are not important. Size is very important. The AD9754 is 700 mils
> long, not a small part, and you'd need two of them.
>
> But I do agree it is not a good idea unless you really need it.
>
> By the way, I have designed a production-quality delta sigma D/A. It
> went in over 17M Sony Ericsson phones. But it was implemented in
> software on a TMS320C54x, not FPGA. You can see a presentation I
> made on it at the first comp.dsp conference here:
>
>  http://www.digitalsignallabs.com/presentation.pdf
> --

Nice presentation, thanks. Not a lot of meat but it looks like you're
deep enough into the science that you have a good handle on the
oversampling ratio you'll need to support the 2Msps IQ rates as well
as the filter order you're targeting. You should know the pulse size
for the SOQPSK method you're pursuing (-A, -B, -TK?) so you know how
much history you'd need for a lookup of symbol to output data.

Here's something I hadn't considered: since FPGAs are far from analog
components, are there small serializers that have significantly better
jitter and amplitude characteristics such that you could broad-load 10
or 20 bits at a time from the FPGA and shoot those out at multi-
gigabit rates, replacing the retime and relevel circuit I was
suggesting before?

I still think the 1-bit oversampled lookups will be problematic if at
least the first order residual isn't matched in the multi-order delta
sigma modulator. Am I being paranoid?

I like how this could come together (in my own mind): a few symbols
of 2-bit I/Q history, simple lookups pushing data to external
serializer, pre-calculated bandpass delta-sigma stream produces I/Q
modulated carrier directly to high IF, single filter to recover a
clean IF, simple mixer rather than I/Q modulators, SAW filter.

And I'm not sure about the bandpass style delta sigma modulator but I
think they're well developed.
From: Michael S on 29 Mar 2010 08:03
On Mar 29, 2:33 am, Randy Yates <ya...(a)ieee.org> wrote:
> Michael S <already5cho...(a)yahoo.com> writes:
> > On Mar 28, 9:27 pm, Symon <symon_bre...(a)hotmail.com> wrote:
> >> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...(a)ieee.org> wrote:
> >> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator
> >> >> that already has a high (baseband) sample rate - around 40-80 MHz.
>
> >> > That's a very bad idea.
> >> > For your sort of application homemade delta-sigma DAC can't match
> >> > combination of price, SNR, SFDR and power provided by something like
> >> > AD9754.
>
> >> I'm pretty sure on price and power (I assume efficiency?) his solution
> >> does match your suggested alternative given that, from details in his
> >> previous postings on this newsgroup, the FPGA/CPLD device is a sunk
> >> cost. I agree with your other acronyms though!
> >> Cheers, Syms.
>
> > At what rate do you have to generate pulses to build, say 12-bit 80
> > MSPS? I don't know the exact answer but pretty sure that the required
> > rate is way above capabilities of CPLDs and likely above what's
> > possible with smallest FPGAs.
> > You would need FPGA with the serializer implemented in hardware So,
> > still on the digital side, you are pushed from something like $4 up to
> > something like $30 or more. The difference already pays for several
> > AD9754s both in money and in power consumption. Now, consider all the
> > analog parts that you need to filter you pulse train into nice analog
> > signal. Since, even with mid-range FPGA you will have relatively
> > modest oversampling (factor of 15 or something like that) the analog
> > filter will have to be rather sharp and probably high order. It would
> > cost you more money and more power.
>
> > As I said above, implementing high speed DAC in programmable logic
> > device is very bad idea.
> > Implementing voice-grade (voice, not audio) DAC sounds less crazy but
> > from point of view of economics, power and board real estate even that
> > is more often than not a losing proposition.
>
> Michael,
>
> "Bad" is relative to your criteria. Hint: in my application, cost and
> power are not important. Size is very important. The AD9754 is 700 mils
> long, not a small part, and you'd need two of them.

Not as small part in SOIC, but pretty small in TSSO packet. Anyway,
AD9754 is just an example of the sort of external DAC we compare
against. For practical IQ application you are likely to pick AD9116/
AD9117. And don't forget the analog components required by delta-sigma
take space too.
However if the power and cost is less important but the size is
paramount, may be, direct conversion to IF with really fast DAC is a
better idea?

>
> But I do agree it is not a good idea unless you really need it.
>
> By the way, I have designed a production-quality delta sigma D/A. It
> went in over 17M Sony Ericsson phones. But it was implemented in
> software on a TMS320C54x, not FPGA. You can see a presentation I
> made on it at the first comp.dsp conference here:
>
> http://www.digitalsignallabs.com/presentation.pdf

It's not clear from presentation but I suppose that you are talking
about voice-grade DAC or may be something a little worse than the
classic 100 to 3200 Hz voice grade that was considered acceptable in
10 y.o. wireless phones.
Not much of relationship with bandwidth and phase linearity
requirements of 20 Mbps QPSK transmitter.

> --
> Randy Yates % "I met someone who looks alot like you,
> Digital Signal Labs % she does the things you do,
> mailto://ya...(a)ieee.org % but she is an IBM."http://www.digitalsignallabs.com% 'Yours Truly, 2095', *Time*, ELO

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