Memory Blocks in Arria II GX Devices - mixed port read during write
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From: srikanth srikanth on 15 Mar 2010 07:18 Hi, We have generated altera ram ip (RAM: 2-port) from Memory Compiler in MegaWizard Manager. We are operating in mode Mixed-Port Read-During- Write as mentioned in aiigx_51003.pdf (pg no:3-18, fig no:3-20). When we simulate this ram in modelsim the behavior of ram in this mode is not matching with section 3-20. of aiigx_51003.pdf The use case in this mode is one port reading and the other port writing to the same address location with the same clock. We have chosen option: old data. In old data mode, a read-during-write operation to different ports causes the RAM outputs to reflect the old data at that address location. But we are seeing don't care 'X' at the output in our simulation mode. Please suggest me to solve this kind of issue. We are simulating the way it is mentioned in fig no:3-20 of aiigx_51003.pdf Regards, Srikanth |