Microblaze FSL peripheral problem
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From: dotnetters on 18 Mar 2006 00:05 Hello All! We are newbies to FPGAs and VHDL. We're doing a project on it and we need to have custom hardware for it. We then settled for the FSL solution. We are just starting to work on it.. We wanted to have a very primitive ALU kind of a thing. We set out editing the a template file generated when we create a new peripheral on XPS (We use EDK7.1), which gets 8 input words and returns their sum. We modified the VHDL code to want to it to work this way: get an opcode, get two operands and return the sum or difference based on the opcode. Something kind of this: if(opcode == ) return a+b; else return a * b; But its not working. We tried out many things, but in vain. I'm copy-n-paste-ing the VHDL code here and also the C file. Please help us figure out the problem: ------------------------------------------------------------------------------ -- MyIP - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY ** -- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR ** -- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND ** -- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES ** -- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: MyIP -- Version: 1.00.a -- Description: Example FSL core (VHDL). -- Date: Mon Mar 13 20:23:40 2006 (by Create and Import Peripheral Wizard Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------------- -- -- -- Definition of Ports -- FSL_Clk : Synchronous clock -- FSL_Rst : System reset, should always come from FSL bus -- FSL_S_Clk : Slave asynchronous clock -- FSL_S_Read : Read signal, requiring next available input to be read -- FSL_S_Data : Input data -- FSL_S_CONTROL : Control Bit, indicating the input data are control word -- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus -- FSL_M_Clk : Master asynchronous clock -- FSL_M_Write : Write signal, enabling writing to output FSL bus -- FSL_M_Data : Output data -- FSL_M_Control : Control Bit, indicating the output data are contol word -- FSL_M_Full : Full Bit, indicating output FSL bus is full -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ -- Entity Section ------------------------------------------------------------------------------ entity MyIP is port ( -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add or delete. FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of FSL_Clk : signal is "Clk"; attribute SIGIS of FSL_S_Clk : signal is "Clk"; attribute SIGIS of FSL_M_Clk : signal is "Clk"; end MyIP; ------------------------------------------------------------------------------ -- Architecture Section ------------------------------------------------------------------------------ -- In this section, we povide an example implementation of ENITY MyIP -- that does the following: -- -- 1. Read all inputs -- 2. Add each input to the contents of register 'sum' which -- acts as an accumulator -- 3. After all the inputs have been read, write out the -- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times -- -- You will need to modify this example or implement a new architecture for -- ENTITY MyIP to implement your coprocessor architecture EXAMPLE of MyIP is -- Total number of input data. constant NUMBER_OF_INPUT_WORDS : natural := 3; -- Total number of output data constant NUMBER_OF_OUTPUT_WORDS : natural := 1; type STATE_TYPE is (Idle, Read_Operands, Write_Outputs); signal state : STATE_TYPE; -- Accumulator to hold sum of inputs read at any point in time signal sum : std_logic_vector(0 to 31); signal op : std_logic_vector(0 to 31); -- Counters to store the number inputs read & outputs written signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1; signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1; -- Stack definition starts ======================= -- The Stack constant MAXSTACK:INTEGER := 256; -- the max stack file length type stack_file is array (MAXSTACK-1 downto 0) of std_logic_vector(0 to 31); -- 256 entry stack. signal TheStack : stack_file; -- Stack variables and pointers signal sp : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; -- the stack pointer signal localStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; signal argsStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; type StackState is (CTRL, DATA, ARGSDATA, LDLOCS); signal nextState : StackState := CTRL; -- first to start with: Ctrl signal. -- Stack definition ends ========================= begin -- CAUTION: -- The sequence in which data are read in and written out should be -- consistant with the sequence they are written and read in the -- driver's MyIP.c file FSL_S_Read <= FSL_S_Exists when state = Read_Operands else '0'; FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0'; FSL_M_Data <= sum; The_SW_accelerator : process (FSL_Clk) is begin -- process The_SW_accelerator if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge if FSL_Rst = '1' then -- Synchronous reset (active high) -- CAUTION: make sure your reset polarity is consistant with the -- system reset polarity state <= Idle; nr_of_reads <= 0; nr_of_writes <= 0; sum <= (others => '0'); else case state is when Idle => if (FSL_S_Exists = '1') then op <= std_logic_vector(unsigned(FSL_S_Data)); state <= Read_Operands; nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1; sum <= (others => '0'); end if; when Read_Operands => if (FSL_S_Exists = '1') then if (unsigned(op) = 0) then sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data)); elsif (unsigned(op) = 1) then sum <= std_logic_vector(unsigned(sum) * unsigned(FSL_S_Data)); else sum <= "10101010101010101010101010101010"; end if; if (nr_of_reads = 0) then state <= Write_Outputs; nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1; else nr_of_reads <= nr_of_reads - 1; state <= Read_Operands; end if; end if; when Write_Outputs => if (nr_of_writes = 0) then state <= Idle; else if (FSL_M_Full = '0') then nr_of_writes <= nr_of_writes - 1; end if; end if; end case; end if; end if; end process The_SW_accelerator; end architecture EXAMPLE; And this is the C file: /* * * Copyright (c) 2004 Xilinx, Inc. All rights reserved. * * Xilinx, Inc. * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. */ /* * Xilinx EDK 7.1.2 EDK_H.12.5.1 * * This file is a sample test application * * This application is intended to test and/or illustrate some * functionality of your system. The contents of this file may * vary depending on the IP in your system and may use existing * IP driver functions. These drivers will be generated in your * XPS project when you run the "Generate Libraries" menu item * in XPS. * * Your XPS project directory is at: * C:\Projects */ // Located in: microblaze_0/include/xparameters.h #include "xparameters.h" #include "mb_interface.h" #include "xutil.h" //==================================================== int main (void) { print("-- Entering main() --\r\n"); int i = 0, k=0, r=0, j=0; /* * MemoryTest routine will not be run for the memory at * 0x00000000 (dlmb_cntlr) * because it is being used to hold a part of this application program */ microblaze_bwrite_datafsl(0,0); microblaze_bwrite_datafsl(304,0); microblaze_bwrite_datafsl(1,0); for(i=0;i<100;i++); microblaze_nbread_datafsl(j,1); xil_printf("%d; ",j); microblaze_bwrite_datafsl(1,0); microblaze_bwrite_datafsl(1,0); microblaze_bwrite_datafsl(1,0); for(i=0;i<100;i++); microblaze_nbread_datafsl(j,1); xil_printf("%d; ",j); microblaze_bwrite_datafsl(0,0); microblaze_bwrite_datafsl(22,0); microblaze_bwrite_datafsl(2,0); microblaze_nbread_datafsl(j,1); xil_printf("%d; ",j); print("-- Exiting main() --\r\n"); return 0; } Its not working as expected. Please help. Thanks. -- Dotnetters.
From: Ralf Hildebrandt on 18 Mar 2006 02:36 dotnetters(a)gmail.com wrote: > We are newbies to FPGAs and VHDL. .... > We modified the VHDL code to > want to it to work this way: get an opcode, get two operands and return > the sum or difference based on the opcode. Something kind of this: > if(opcode == ) > return a+b; > else > return a * b; > But its not working. This sounds to me to be a pure VHDL problem. -> comp.lang.vhdl You seek for a pure combinational solution (add, mul, mux) and post a code of a state machine, which is sequential. What do you want? ;-) Do your try to get something running by modifying examples so that it fits your requirements? I would not recommend this. Use examples as ideas and guidelines, but write your own code. Wouldn't it be a good idea to post a _minimal example_ of your problem? Ralf
From: dotnetters on 18 Mar 2006 03:08 Ralf, Sorry, we were right from the start doubtful whether this was the right group to ask for clarification. But since we had problems with FSL, which was more to the MicroBlaze side, we thought it would be fine to do so.. And obviously, we were wrong.. Anyway, thanks. Cheers, everyone.. -- DotNetters
From: Sylvain Munaut on 18 Mar 2006 03:52 Your first VHDL looks wrong ... You put : FSL_S_Read <= FSL_S_Exists when state = Read_Operands else '0'; But you read data during the IDLE cycle as well, since you read the operation to do during that cycle. So it should be FSL_S_Read <= FSL_S_Exists when (state = Read_Operands) or (state = Idle) else '0'; But then you don't need to read 3 data during the Read_Operands state but only 2. So you should use constant NUMBER_OF_INPUT_WORDS : natural := 2; You made theses mistakes because you tries to modify code you didn't understand properly. You should have written your peripheral from scratch, using the demo code to see how FSL works. Sylvain dotnetters(a)gmail.com wrote: > Hello All! > We are newbies to FPGAs and VHDL. We're doing a project on it and we > need to have custom hardware for it. We then settled for the FSL > solution. We are just starting to work on it.. We wanted to have a very > primitive ALU kind of a thing. We set out editing the a template file > generated when we create a new peripheral on XPS (We use EDK7.1), which > gets 8 input words and returns their sum. We modified the VHDL code to > want to it to work this way: get an opcode, get two operands and return > the sum or difference based on the opcode. Something kind of this: > if(opcode == ) > return a+b; > else > return a * b; > But its not working. We tried out many things, but in vain. I'm > copy-n-paste-ing the VHDL code here and also the C file. Please help us > figure out the problem: > > ------------------------------------------------------------------------------ > -- MyIP - entity/architecture pair > ------------------------------------------------------------------------------ > -- > -- > *************************************************************************** > -- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > ** > -- ** > ** > -- ** Xilinx, Inc. > ** > -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" > ** > -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND > ** > -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, > ** > -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, > ** > -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION > ** > -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, > ** > -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE > ** > -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY > ** > -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE > ** > -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR > ** > -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF > ** > -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS > ** > -- ** FOR A PARTICULAR PURPOSE. > ** > -- ** > ** > -- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE > SOLELY ** > -- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR > ** > -- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES > AND ** > -- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES > ** > -- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. > ** > -- ** > ** > -- > *************************************************************************** > -- > ------------------------------------------------------------------------------ > -- Filename: MyIP > -- Version: 1.00.a > -- Description: Example FSL core (VHDL). > -- Date: Mon Mar 13 20:23:40 2006 (by Create and Import > Peripheral Wizard Wizard) > -- VHDL Standard: VHDL'93 > ------------------------------------------------------------------------------ > -- Naming Conventions: > -- active low signals: "*_n" > -- clock signals: "clk", "clk_div#", "clk_#x" > -- reset signals: "rst", "rst_n" > -- generics: "C_*" > -- user defined types: "*_TYPE" > -- state machine next state: "*_ns" > -- state machine current state: "*_cs" > -- combinatorial signals: "*_com" > -- pipelined or register delay signals: "*_d#" > -- counter signals: "*cnt*" > -- clock enable signals: "*_ce" > -- internal version of output port: "*_i" > -- device pins: "*_pin" > -- ports: "- Names begin with > Uppercase" > -- processes: "*_PROCESS" > -- component instantiations: "<ENTITY_>I_<#|FUNC>" > ------------------------------------------------------------------------------ > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > ------------------------------------------------------------------------------------- > -- > -- > -- Definition of Ports > -- FSL_Clk : Synchronous clock > -- FSL_Rst : System reset, should always come from FSL bus > -- FSL_S_Clk : Slave asynchronous clock > -- FSL_S_Read : Read signal, requiring next available input to be > read > -- FSL_S_Data : Input data > -- FSL_S_CONTROL : Control Bit, indicating the input data are control > word > -- FSL_S_Exists : Data Exist Bit, indicating data exist in the input > FSL bus > -- FSL_M_Clk : Master asynchronous clock > -- FSL_M_Write : Write signal, enabling writing to output FSL bus > -- FSL_M_Data : Output data > -- FSL_M_Control : Control Bit, indicating the output data are contol > word > -- FSL_M_Full : Full Bit, indicating output FSL bus is full > -- > ------------------------------------------------------------------------------- > > ------------------------------------------------------------------------------ > -- Entity Section > ------------------------------------------------------------------------------ > > entity MyIP is > port > ( > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add or delete. > FSL_Clk : in std_logic; > FSL_Rst : in std_logic; > FSL_S_Clk : out std_logic; > FSL_S_Read : out std_logic; > FSL_S_Data : in std_logic_vector(0 to 31); > FSL_S_Control : in std_logic; > FSL_S_Exists : in std_logic; > FSL_M_Clk : out std_logic; > FSL_M_Write : out std_logic; > FSL_M_Data : out std_logic_vector(0 to 31); > FSL_M_Control : out std_logic; > FSL_M_Full : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > ); > > attribute SIGIS : string; > attribute SIGIS of FSL_Clk : signal is "Clk"; > attribute SIGIS of FSL_S_Clk : signal is "Clk"; > attribute SIGIS of FSL_M_Clk : signal is "Clk"; > > end MyIP; > > ------------------------------------------------------------------------------ > -- Architecture Section > ------------------------------------------------------------------------------ > > -- In this section, we povide an example implementation of ENITY MyIP > -- that does the following: > -- > -- 1. Read all inputs > -- 2. Add each input to the contents of register 'sum' which > -- acts as an accumulator > -- 3. After all the inputs have been read, write out the > -- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS > times > -- > -- You will need to modify this example or implement a new architecture > for > -- ENTITY MyIP to implement your coprocessor > > architecture EXAMPLE of MyIP is > > -- Total number of input data. > constant NUMBER_OF_INPUT_WORDS : natural := 3; > > -- Total number of output data > constant NUMBER_OF_OUTPUT_WORDS : natural := 1; > > type STATE_TYPE is (Idle, Read_Operands, Write_Outputs); > > signal state : STATE_TYPE; > > -- Accumulator to hold sum of inputs read at any point in time > signal sum : std_logic_vector(0 to 31); > signal op : std_logic_vector(0 to 31); > > -- Counters to store the number inputs read & outputs written > signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1; > signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1; > > -- Stack definition starts ======================= > -- The Stack > constant MAXSTACK:INTEGER := 256; -- the max stack file length > type stack_file is array (MAXSTACK-1 downto 0) of > std_logic_vector(0 to 31); -- 256 entry stack. > signal TheStack : stack_file; > > -- Stack variables and pointers > signal sp : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; -- > the stack pointer > signal localStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') > ; > signal argsStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; > > type StackState is (CTRL, DATA, ARGSDATA, LDLOCS); > signal nextState : StackState := CTRL; -- first to start with: Ctrl > signal. > -- Stack definition ends ========================= > > > begin > -- CAUTION: > -- The sequence in which data are read in and written out should be > -- consistant with the sequence they are written and read in the > -- driver's MyIP.c file > > FSL_S_Read <= FSL_S_Exists when state = Read_Operands else '0'; > FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0'; > > FSL_M_Data <= sum; > > The_SW_accelerator : process (FSL_Clk) is > begin -- process The_SW_accelerator > if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge > if FSL_Rst = '1' then -- Synchronous reset (active > high) > -- CAUTION: make sure your reset polarity is consistant with > the > -- system reset polarity > state <= Idle; > nr_of_reads <= 0; > nr_of_writes <= 0; > sum <= (others => '0'); > else > case state is > when Idle => > if (FSL_S_Exists = '1') then > op <= std_logic_vector(unsigned(FSL_S_Data)); > state <= Read_Operands; > nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1; > sum <= (others => '0'); > end if; > > when Read_Operands => > if (FSL_S_Exists = '1') then > if (unsigned(op) = 0) then > sum <= std_logic_vector(unsigned(sum) + > unsigned(FSL_S_Data)); > elsif (unsigned(op) = 1) then > sum <= std_logic_vector(unsigned(sum) * > unsigned(FSL_S_Data)); > else > sum <= "10101010101010101010101010101010"; > end if; > if (nr_of_reads = 0) then > state <= Write_Outputs; > nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1; > else > nr_of_reads <= nr_of_reads - 1; > state <= Read_Operands; > end if; > end if; > > when Write_Outputs => > if (nr_of_writes = 0) then > state <= Idle; > else > if (FSL_M_Full = '0') then > nr_of_writes <= nr_of_writes - 1; > end if; > end if; > end case; > end if; > end if; > end process The_SW_accelerator; > end architecture EXAMPLE; > > > And this is the C file: > /* > * * Copyright (c) 2004 Xilinx, Inc. All rights reserved. > * > * Xilinx, Inc. > * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A > * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS > * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR > * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS > IMPLEMENTATION > * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE > * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION > * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO > * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO > * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE > * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY > * AND FITNESS FOR A PARTICULAR PURPOSE. > */ > > /* > * Xilinx EDK 7.1.2 EDK_H.12.5.1 > * > * This file is a sample test application > * > * This application is intended to test and/or illustrate some > * functionality of your system. The contents of this file may > * vary depending on the IP in your system and may use existing > * IP driver functions. These drivers will be generated in your > * XPS project when you run the "Generate Libraries" menu item > * in XPS. > * > * Your XPS project directory is at: > * C:\Projects > */ > > > // Located in: microblaze_0/include/xparameters.h > #include "xparameters.h" > > #include "mb_interface.h" > > #include "xutil.h" > > //==================================================== > > int main (void) { > > > print("-- Entering main() --\r\n"); > int i = 0, k=0, r=0, j=0; > > /* > * MemoryTest routine will not be run for the memory at > * 0x00000000 (dlmb_cntlr) > * because it is being used to hold a part of this application > program > */ > > microblaze_bwrite_datafsl(0,0); > microblaze_bwrite_datafsl(304,0); > microblaze_bwrite_datafsl(1,0); > > for(i=0;i<100;i++); > microblaze_nbread_datafsl(j,1); > xil_printf("%d; ",j); > > microblaze_bwrite_datafsl(1,0); > microblaze_bwrite_datafsl(1,0); > microblaze_bwrite_datafsl(1,0); > > for(i=0;i<100;i++); > microblaze_nbread_datafsl(j,1); > xil_printf("%d; ",j); > > microblaze_bwrite_datafsl(0,0); > microblaze_bwrite_datafsl(22,0); > microblaze_bwrite_datafsl(2,0); > microblaze_nbread_datafsl(j,1); > xil_printf("%d; ",j); > > print("-- Exiting main() --\r\n"); > return 0; > } > > Its not working as expected. Please help. > > Thanks. > -- Dotnetters. >
From: Göran Bilski on 20 Mar 2006 04:31
Can you explore "not working as intended"? The C code looks a little strange. You write on FSL channel 0 but read on FSL channel 1. Is that how you have connected the FSL accelerator to MicroBlaze? G?ran Bilski dotnetters(a)gmail.com wrote: > Hello All! > We are newbies to FPGAs and VHDL. We're doing a project on it and we > need to have custom hardware for it. We then settled for the FSL > solution. We are just starting to work on it.. We wanted to have a very > primitive ALU kind of a thing. We set out editing the a template file > generated when we create a new peripheral on XPS (We use EDK7.1), which > gets 8 input words and returns their sum. We modified the VHDL code to > want to it to work this way: get an opcode, get two operands and return > the sum or difference based on the opcode. Something kind of this: > if(opcode == ) > return a+b; > else > return a * b; > But its not working. We tried out many things, but in vain. I'm > copy-n-paste-ing the VHDL code here and also the C file. Please help us > figure out the problem: > > ------------------------------------------------------------------------------ > -- MyIP - entity/architecture pair > ------------------------------------------------------------------------------ > -- > -- > *************************************************************************** > -- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > ** > -- ** > ** > -- ** Xilinx, Inc. > ** > -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" > ** > -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND > ** > -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, > ** > -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, > ** > -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION > ** > -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, > ** > -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE > ** > -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY > ** > -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE > ** > -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR > ** > -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF > ** > -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS > ** > -- ** FOR A PARTICULAR PURPOSE. > ** > -- ** > ** > -- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE > SOLELY ** > -- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR > ** > -- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES > AND ** > -- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES > ** > -- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. > ** > -- ** > ** > -- > *************************************************************************** > -- > ------------------------------------------------------------------------------ > -- Filename: MyIP > -- Version: 1.00.a > -- Description: Example FSL core (VHDL). > -- Date: Mon Mar 13 20:23:40 2006 (by Create and Import > Peripheral Wizard Wizard) > -- VHDL Standard: VHDL'93 > ------------------------------------------------------------------------------ > -- Naming Conventions: > -- active low signals: "*_n" > -- clock signals: "clk", "clk_div#", "clk_#x" > -- reset signals: "rst", "rst_n" > -- generics: "C_*" > -- user defined types: "*_TYPE" > -- state machine next state: "*_ns" > -- state machine current state: "*_cs" > -- combinatorial signals: "*_com" > -- pipelined or register delay signals: "*_d#" > -- counter signals: "*cnt*" > -- clock enable signals: "*_ce" > -- internal version of output port: "*_i" > -- device pins: "*_pin" > -- ports: "- Names begin with > Uppercase" > -- processes: "*_PROCESS" > -- component instantiations: "<ENTITY_>I_<#|FUNC>" > ------------------------------------------------------------------------------ > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > ------------------------------------------------------------------------------------- > -- > -- > -- Definition of Ports > -- FSL_Clk : Synchronous clock > -- FSL_Rst : System reset, should always come from FSL bus > -- FSL_S_Clk : Slave asynchronous clock > -- FSL_S_Read : Read signal, requiring next available input to be > read > -- FSL_S_Data : Input data > -- FSL_S_CONTROL : Control Bit, indicating the input data are control > word > -- FSL_S_Exists : Data Exist Bit, indicating data exist in the input > FSL bus > -- FSL_M_Clk : Master asynchronous clock > -- FSL_M_Write : Write signal, enabling writing to output FSL bus > -- FSL_M_Data : Output data > -- FSL_M_Control : Control Bit, indicating the output data are contol > word > -- FSL_M_Full : Full Bit, indicating output FSL bus is full > -- > ------------------------------------------------------------------------------- > > ------------------------------------------------------------------------------ > -- Entity Section > ------------------------------------------------------------------------------ > > entity MyIP is > port > ( > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add or delete. > FSL_Clk : in std_logic; > FSL_Rst : in std_logic; > FSL_S_Clk : out std_logic; > FSL_S_Read : out std_logic; > FSL_S_Data : in std_logic_vector(0 to 31); > FSL_S_Control : in std_logic; > FSL_S_Exists : in std_logic; > FSL_M_Clk : out std_logic; > FSL_M_Write : out std_logic; > FSL_M_Data : out std_logic_vector(0 to 31); > FSL_M_Control : out std_logic; > FSL_M_Full : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > ); > > attribute SIGIS : string; > attribute SIGIS of FSL_Clk : signal is "Clk"; > attribute SIGIS of FSL_S_Clk : signal is "Clk"; > attribute SIGIS of FSL_M_Clk : signal is "Clk"; > > end MyIP; > > ------------------------------------------------------------------------------ > -- Architecture Section > ------------------------------------------------------------------------------ > > -- In this section, we povide an example implementation of ENITY MyIP > -- that does the following: > -- > -- 1. Read all inputs > -- 2. Add each input to the contents of register 'sum' which > -- acts as an accumulator > -- 3. After all the inputs have been read, write out the > -- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS > times > -- > -- You will need to modify this example or implement a new architecture > for > -- ENTITY MyIP to implement your coprocessor > > architecture EXAMPLE of MyIP is > > -- Total number of input data. > constant NUMBER_OF_INPUT_WORDS : natural := 3; > > -- Total number of output data > constant NUMBER_OF_OUTPUT_WORDS : natural := 1; > > type STATE_TYPE is (Idle, Read_Operands, Write_Outputs); > > signal state : STATE_TYPE; > > -- Accumulator to hold sum of inputs read at any point in time > signal sum : std_logic_vector(0 to 31); > signal op : std_logic_vector(0 to 31); > > -- Counters to store the number inputs read & outputs written > signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1; > signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1; > > -- Stack definition starts ======================= > -- The Stack > constant MAXSTACK:INTEGER := 256; -- the max stack file length > type stack_file is array (MAXSTACK-1 downto 0) of > std_logic_vector(0 to 31); -- 256 entry stack. > signal TheStack : stack_file; > > -- Stack variables and pointers > signal sp : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; -- > the stack pointer > signal localStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') > ; > signal argsStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; > > type StackState is (CTRL, DATA, ARGSDATA, LDLOCS); > signal nextState : StackState := CTRL; -- first to start with: Ctrl > signal. > -- Stack definition ends ========================= > > > begin > -- CAUTION: > -- The sequence in which data are read in and written out should be > -- consistant with the sequence they are written and read in the > -- driver's MyIP.c file > > FSL_S_Read <= FSL_S_Exists when state = Read_Operands else '0'; > FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0'; > > FSL_M_Data <= sum; > > The_SW_accelerator : process (FSL_Clk) is > begin -- process The_SW_accelerator > if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge > if FSL_Rst = '1' then -- Synchronous reset (active > high) > -- CAUTION: make sure your reset polarity is consistant with > the > -- system reset polarity > state <= Idle; > nr_of_reads <= 0; > nr_of_writes <= 0; > sum <= (others => '0'); > else > case state is > when Idle => > if (FSL_S_Exists = '1') then > op <= std_logic_vector(unsigned(FSL_S_Data)); > state <= Read_Operands; > nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1; > sum <= (others => '0'); > end if; > > when Read_Operands => > if (FSL_S_Exists = '1') then > if (unsigned(op) = 0) then > sum <= std_logic_vector(unsigned(sum) + > unsigned(FSL_S_Data)); > elsif (unsigned(op) = 1) then > sum <= std_logic_vector(unsigned(sum) * > unsigned(FSL_S_Data)); > else > sum <= "10101010101010101010101010101010"; > end if; > if (nr_of_reads = 0) then > state <= Write_Outputs; > nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1; > else > nr_of_reads <= nr_of_reads - 1; > state <= Read_Operands; > end if; > end if; > > when Write_Outputs => > if (nr_of_writes = 0) then > state <= Idle; > else > if (FSL_M_Full = '0') then > nr_of_writes <= nr_of_writes - 1; > end if; > end if; > end case; > end if; > end if; > end process The_SW_accelerator; > end architecture EXAMPLE; > > > And this is the C file: > /* > * * Copyright (c) 2004 Xilinx, Inc. All rights reserved. > * > * Xilinx, Inc. > * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A > * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS > * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR > * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS > IMPLEMENTATION > * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE > * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION > * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO > * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO > * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE > * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY > * AND FITNESS FOR A PARTICULAR PURPOSE. > */ > > /* > * Xilinx EDK 7.1.2 EDK_H.12.5.1 > * > * This file is a sample test application > * > * This application is intended to test and/or illustrate some > * functionality of your system. The contents of this file may > * vary depending on the IP in your system and may use existing > * IP driver functions. These drivers will be generated in your > * XPS project when you run the "Generate Libraries" menu item > * in XPS. > * > * Your XPS project directory is at: > * C:\Projects > */ > > > // Located in: microblaze_0/include/xparameters.h > #include "xparameters.h" > > #include "mb_interface.h" > > #include "xutil.h" > > //==================================================== > > int main (void) { > > > print("-- Entering main() --\r\n"); > int i = 0, k=0, r=0, j=0; > > /* > * MemoryTest routine will not be run for the memory at > * 0x00000000 (dlmb_cntlr) > * because it is being used to hold a part of this application > program > */ > > microblaze_bwrite_datafsl(0,0); > microblaze_bwrite_datafsl(304,0); > microblaze_bwrite_datafsl(1,0); > > for(i=0;i<100;i++); > microblaze_nbread_datafsl(j,1); > xil_printf("%d; ",j); > > microblaze_bwrite_datafsl(1,0); > microblaze_bwrite_datafsl(1,0); > microblaze_bwrite_datafsl(1,0); > > for(i=0;i<100;i++); > microblaze_nbread_datafsl(j,1); > xil_printf("%d; ",j); > > microblaze_bwrite_datafsl(0,0); > microblaze_bwrite_datafsl(22,0); > microblaze_bwrite_datafsl(2,0); > microblaze_nbread_datafsl(j,1); > xil_printf("%d; ",j); > > print("-- Exiting main() --\r\n"); > return 0; > } > > Its not working as expected. Please help. > > Thanks. > -- Dotnetters. > |