From: melinda on
Hi all,

I am simulating a entity with Modelsim (v6.5c). Modelsim
only displays the input/output signals of the simulated top entity.

When I run simulation Modelsim displays only changes of input/output
signals of the top entity verilog module i.e. testbench (in objects window
i.e. in wave window), but nothing happening with signals declared in the
instantiated verilog modules.
(PS: In Cadence SimVision, I know that I was able to see changes of all
signals in testbench and also in instantiated verilog modules, in wave
window)

Is there a way of viewing the internal signals declared in the instantiated
verilog modules in Modelsim in wave window?

Thanks very much

Regards



From: NigelE on
On Nov 3, 2:29 pm, "melinda" <melinda.m...(a)gmail.com> wrote:
> Hi all,
>
> I am simulating a entity with Modelsim (v6.5c). Modelsim
> only displays the input/output signals of the simulated top entity.
>
> When I run simulation Modelsim displays only changes of input/output
> signals of the top entity verilog module i.e. testbench (in objects window
> i.e. in wave window), but nothing happening with signals declared in the
> instantiated verilog modules.
> (PS: In Cadence SimVision, I know that I was able to see changes of all
> signals in testbench and also in instantiated verilog modules, in wave
> window)
>
> Is there a way of viewing the internal signals declared in the instantiated
> verilog modules in Modelsim in wave window?
>
> Thanks very much
>
> Regards

Hi Melinda

I assume you're using ModelSim SE?

By default, SE optimizes the design for maximum performance, which
includes removing the capability to log internal nodes.
This optimization is done by the vopt command, which you can call
explicitly after compilation else is run implicitly when you start
vsim (you'll see "** Note: (vsim-3812) Design is being optimized..."
in the transcript).

To enable the ability to log internal signals you must give vopt some
additional parameters
The following will enable access to all objects in the whole design

Explicit vopt:
vopt my_top +acc -o top_opt
vsim top_opt

Implicit vopt:
vsim my_top -voptargs="+acc"

Obviously, this will slow the simulation down compared to the fully
optimised design.
You can control what is 'accessible' (object types / modules /
instances etc) by adding more options to the vopt command (see the
User Manual for details) if you want to balance debug vs. performance.

Hope this helps

- Nigel
From: melinda on
Thanks Nigel,

I was try that, but I'm still not able to see any changes of signals in
instantiated modules(in wave form window).

When I put some signals from instantiated verilog modules to wave form
window, after I hit "run" simulation those signals remain X.

Do you have any idea why is that so?

Best Regards

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From: Mike Treseler on
melinda wrote:

> Is there a way of viewing the internal signals declared in the instantiated
> verilog modules in Modelsim in wave window?

add wave -r /*
From: Brad Smallridge on
Hi Melinda,

Can we assume that you are adding the internal signals with
some GUI commands like this:
View - Workspace - browse for your entitiy - Right Click - Add - Add to Wave

Brad Smallridge
AiVision

"melinda" <melinda.mel3(a)gmail.com> wrote in message
news:Soudna7GPeTPo23XnZ2dnUVZ_vWdnZ2d(a)giganews.com...
> Hi all,
>
> I am simulating a entity with Modelsim (v6.5c). Modelsim
> only displays the input/output signals of the simulated top entity.
>
> When I run simulation Modelsim displays only changes of input/output
> signals of the top entity verilog module i.e. testbench (in objects window
> i.e. in wave window), but nothing happening with signals declared in the
> instantiated verilog modules.
> (PS: In Cadence SimVision, I know that I was able to see changes of all
> signals in testbench and also in instantiated verilog modules, in wave
> window)
>
> Is there a way of viewing the internal signals declared in the
> instantiated
> verilog modules in Modelsim in wave window?
>
> Thanks very much
>
> Regards
>
>
>