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From: glen herrmannsfeldt on 27 Mar 2010 13:39
John_H <newsgroup(a)johnhandwork.com> wrote:
> On Mar 26, 11:39?pm, Randy Yates <ya...(a)ieee.org> wrote:

>> I'm looking for a device that will perform something on
>> the order of hundreds of millions of 12x12 multiplies
>> per second, and I need it small. I only need about
>> 30-40 pins of I/O.
(snip)

> How do you expect to get hundreds of millions of operands onto
> and off the chip through 30-40 IO?


That would be worth knowing, otherwise we have to guess.

I think you can do I/O at 200MHz through many current FPGA,
so he could do one multiplier at 200MHz. Maybe he doesn't
need all the product bits, so 36 I/Os.

My guess, though, is a digital filter doing a succession
of multiplies and adds, in which case the I/O rate could
be much lower. A systolic array multiplier in FPGA logic,
latched at every step, would be very fast and you get pretty
many of them on even a small FPGA. That is, not even using
the block multipliers.

-- glen
From: Randy Yates on 27 Mar 2010 14:29
glen herrmannsfeldt <gah(a)ugcs.caltech.edu> writes:

> John_H <newsgroup(a)johnhandwork.com> wrote:
>> On Mar 26, 11:39?pm, Randy Yates <ya...(a)ieee.org> wrote:
>
>>> I'm looking for a device that will perform something on
>>> the order of hundreds of millions of 12x12 multiplies
>>> per second, and I need it small. I only need about
>>> 30-40 pins of I/O.
> (snip)
>
>> How do you expect to get hundreds of millions of operands onto
>> and off the chip through 30-40 IO?
>
>
> That would be worth knowing, otherwise we have to guess.
>
> I think you can do I/O at 200MHz through many current FPGA,
> so he could do one multiplier at 200MHz. Maybe he doesn't
> need all the product bits, so 36 I/Os.
>
> My guess, though, is a digital filter doing a succession
> of multiplies and adds, in which case the I/O rate could
> be much lower. A systolic array multiplier in FPGA logic,
> latched at every step, would be very fast and you get pretty
> many of them on even a small FPGA. That is, not even using
> the block multipliers.

Hey glen! Nice to see you here!

Sorry, I didn't mean to ignore your (valuable) suggestions. I've heard
the term "systolic array." I guess I'm gonna have to learn about them
now. :)

That is, if John's lookup table approach won't work - that would be
the best, and since the input data is just two bits, it'll probably
be the way to go.
--
Randy Yates % "With time with what you've learned,
Digital Signal Labs % they'll kiss the ground you walk
mailto://yates(a)ieee.org % upon."
http://www.digitalsignallabs.com % '21st Century Man', *Time*, ELO
From: Randy Yates on 27 Mar 2010 14:31
Symon <symon_brewer(a)hotmail.com> writes:

> On 3/27/2010 2:07 PM, Randy Yates wrote:
>>
>>> The coolrunner most probably won't do you any good. There are no
>>> embedded multipliers and no storage beyond the macrocells (at least
>>> per my recollection).
>>
>> That was my feeling too, but I wanted to get a more professional
>> opinion.
>
> Hi Randy,
>
> I don't have much experience of CPLDs, but you may well be able to get
> the multiplier performance you need. Even though a CPLD probably won't
> have dedicated multipliers, there's more than one way to skin a
> cat. Check out distributed arithmetic solutions.
>
> http://www.andraka.com/distribu.htm
>
> Also, you mention FEC. This might use up a fair chunk of hardware, but
> again you can serialise it, if timing permits.
>
> As for your size requirements, I thought the smallest Coolrunner was
> 6x6 = 36mm², too big for your spec.

I was being very loose on the size spec. In fact I don't really (and
my customer doesn't) really have a hard requirement on it, other than
this, the D/As, a PIC, and other support stuff has to fit on a 2.5-in
diameter PCB.
--
Randy Yates % "Rollin' and riding and slippin' and
Digital Signal Labs % sliding, it's magic."
mailto://yates(a)ieee.org %
http://www.digitalsignallabs.com % 'Living' Thing', *A New World Record*, ELO
From: glen herrmannsfeldt on 27 Mar 2010 16:41
Randy Yates <yates(a)ieee.org> wrote:
(someone wrote)

>> As for your size requirements, I thought the smallest Coolrunner was
>> 6x6 = 36mm?, too big for your spec.

> I was being very loose on the size spec. In fact I don't really (and
> my customer doesn't) really have a hard requirement on it, other than
> this, the D/As, a PIC, and other support stuff has to fit on a 2.5-in
> diameter PCB.

You could use a soft processor, such as picoblaze in a Spartan,
instead of the PIC. You might do with less 'support stuff' if
some of that could go in the FPGA.

-- glen
From: -jg on 27 Mar 2010 16:56
On Mar 28, 2:07 am, Randy Yates <ya...(a)ieee.org> wrote:
>
> It's a SOQPSK modulator, so the input data is 2 bits per baud. OK,
> that takes 2 bits. The output is 14-bit I/Q. Ok, thats total 30 bits.
> Add a few for control. Done.

You still have not stated the actual IP and OP data rates, and the
maths-ops needed per delivered output.

Will you be using BGA, or is this QFP and maybe single-row QFN ?

-jg
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