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From: John Larkin on 20 Jun 2010 13:14 On 20 Jun 2010 08:29:57 -0700, Winfield Hill <Winfield_member(a)newsguy.com> wrote: >John Larkin wrote... >> >> On a current design, I had to make my own. I wanted lots of >> overvoltage protection, logic-switchable gains from 0.05 to 256, high >> precision, and at least +-12 volts of common-mode range, 120 dB CMRR >> at high gain. I wound up with a classic 3-opamp diffamp, using an >> LT1124 dual opamp, four Supertex depletion mode fets for protection, a >> discrete string of thinfilm resistors, one DPDT gain switch relay, two >> analog muxes, and an INA154 as the second stage. Two tiny trimpots >> tweak cmrr. Times 16 on one board. I'd love to get all that in a SO-8! > > Indeed. > > What was its CMRR at 1 and 10kHz, that's a tough region. I'm after common-mode rejection for reasonable ground loops (DC, 60 Hz, mild harmonics) and volts of DC from load cell bridges. We tune the CMRR with a 10 volt p-p, 100 Hz square wave applied to both inputs, and the residual, as you turn the tweak pots, looks pretty square. We are currently applying the square wave and looking at the IA output with the gain set to max, using signal averaging on a scope at 2 mv/div, which is 8 uv/div relative to the input. Seems to work. I want to do it all in software, with a lockin-type thing, based on reading our ADC and synchronously detecting it against the cm square wave; if we sell enough of these, it might be worth writing that code. Here it is: http://www.highlandtechnology.com/DSS/V490DS.html The analog stuff pretty much just worked. The big problems were 1. The AD7699 ADC data sheet is, to be polite, terse. The differential inputs are unusual. It is just barely possible, or maybe according to the specs impossible, to actually run it at 500 KHz. A timing diagram might be helpful. 2. I rashly promised 8-pole digital filtering down to 1 Hz, Bessel and Butterworth. That turns out to be non-trivial when you get to 500,000:1 sample/cutoff ratio. Three architectures later, one consultant hired/paid/dumped, great amounts of experiment and simulation and debate, it seems to work. That adventure deserves a thread of its own. One hint: the classic DSP butterfly filter explodes at ratios like this. 3. The lead customer liked the filtering concept so much he asked for two independent filters per channel, one for the realtime data and another for the FIFOs. That's 32 filters and 16 4Kx16 FIFOs and lots of other junk in a Spartan6/45. 4. The Xilinx software is a train wreck, which greatly complicated 2) and 3). Rev 12, supposedly the one that supports Spartan6 properly, is worse than 11. You say "place that flipflop in an i/o block" and it says, after considering the request for five or six hours, "drop dead." We may start using Altera for new designs. I'm tweaking the rev C board layout and finishing up the firmware this weekend. I get interrupted too much at work to let me concentrate on stuff like this. I can't multitask and get serious work done. This is Fathers Day and it's been Meat Weekend. Rubbed Tri-tip last night, BBQ ribs tonight. Nothing green in sight. John
From: langwadt on 21 Jun 2010 14:53 On 20 Jun., 19:14, John Larkin <jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: snip > > 2. I rashly promised 8-pole digital filtering down to 1 Hz, Bessel and > Butterworth. That turns out to be non-trivial when you get to > 500,000:1 sample/cutoff ratio. Three architectures later, one > consultant hired/paid/dumped, great amounts of experiment and > simulation and debate, it seems to work. That adventure deserves a > thread of its own. One hint: the classic DSP butterfly filter explodes > at ratios like this. That is DSP 101 and kinda obvious when you think about it, for a filter to have any effect at 1Hz it needs to have "memory" it that range. with a 500kHz samplerate that either means a very high order or a very high precision standard approach would be decimate the signal to a more resonable sample rate -Lasse
From: John Larkin on 21 Jun 2010 15:58
On Mon, 21 Jun 2010 11:53:34 -0700 (PDT), "langwadt(a)fonz.dk" <langwadt(a)fonz.dk> wrote: >On 20 Jun., 19:14, John Larkin ><jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: >snip >> >> 2. I rashly promised 8-pole digital filtering down to 1 Hz, Bessel and >> Butterworth. That turns out to be non-trivial when you get to >> 500,000:1 sample/cutoff ratio. Three architectures later, one >> consultant hired/paid/dumped, great amounts of experiment and >> simulation and debate, it seems to work. That adventure deserves a >> thread of its own. One hint: the classic DSP butterfly filter explodes >> at ratios like this. > >That is DSP 101 and kinda obvious when you think about it, for a >filter >to have any effect at 1Hz it needs to have "memory" it that range. >with a 500kHz samplerate that either means a very high order or a very >high >precision You'd think that 16 bit data and 1e6:1 sample/cutoff ratio could be accomplished with roughly 36 bit math. > >standard approach would be decimate the signal to a more resonable >sample rate That's one approach: build a chain of filters, clocked at declining rates, and use the early ones to take the stress off the later ones. Switch filters in or out as needed. We could do that, but it's harder to explain to the customers. It's easier to model the product as a lowpass filter followed by a 500 KHz ADC. The classic butterfly explodes violently as the clock:cutoff ratio goes up. Numbers have to subtract to make tiny residuals, and stage gains get absurd. Instead we used a double-integrator filter, essentially a digital simulation of an analog state-variable filter. That gets into trouble much more linearly than the butterfly, and each 2nd order section has a gain of exactly 1. It works using MAC blocks using 18x18 multiplies and a sort of coarse barrel shifter into a 48 bit accumulator. John |