PN SEQUENCE (zero values)
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From: Tim Wescott on 4 Feb 2010 20:09 On Thu, 04 Feb 2010 23:05:18 +0000, glen herrmannsfeldt wrote: > Al Clark <aclark(a)danvillesignal.com> wrote: (snip) > >> You could use an N input NOR connected to each output state. The output >> of the NOR would be 0 for all situations except the all 0 state. You >> could take this value and OR with any one of the output states. This >> would cause an all 0 condition to be changed to one with a single 1 >> state. At this point the states would change to the 2n-1 sequence. Once >> in a 2n-1 sequence, the OR function would never cause a change in the >> next state since you would always be ORing a 0. > >> This is clearly a very bad solution. > > Why is it so bad? If you compare the cost of being in the wrong state > to the cost of the OR gate, is it all that bad? > >> In software, you just initialize a seed to be non zero. > >> In hardware, the VLV solution adds an inverter to the output >> of a flip flop. If you then perform a RESET, you have a >> seed with a single 1, which will avoid the all zero state. > > And if an alpha particle comes through and it does get into the wrong > state then you are stuck. > > -- glen Because that wide wide NOR gate is _expensive_. -- www.wescottdesign.com
From: Tim Wescott on 4 Feb 2010 20:18 On Thu, 04 Feb 2010 14:19:23 -0600, Avier wrote: > just for check > > > IS there any way to produce a PN sequence from all zero intial state. > > that is all zeros in shift regiters Presumably you're implementing this in an LFSR. You have to add logic. By definition a truly _linear_ feedback shift register has multiple modes. If you choose a feedback polynomial that is prime then you get your one maximal-length mode and your zero mode, instead of several shorter ones and a zero one. So you add logic to your LFSR to make it a _non_ linear FSR. The easiest way I can think of to do this is to put a counter on the output of the thing that counts up any time it sees a zero, and resets any time it sees a 1. If the count gets up to 2^N, you've just detected the all-zeros state, and you inject a one into your feedback. Then your FSR isn't in the all-zero state anymore, and life is wonderful. -- www.wescottdesign.com
From: glen herrmannsfeldt on 4 Feb 2010 20:31 Tim Wescott <tim(a)seemywebsite.com> wrote: > On Thu, 04 Feb 2010 23:05:18 +0000, glen herrmannsfeldt wrote: >> Al Clark <aclark(a)danvillesignal.com> wrote: (snip) >>> You could use an N input NOR connected to each output state. The output >>> of the NOR would be 0 for all situations except the all 0 state. (snip) >>> This is clearly a very bad solution. >> Why is it so bad? If you compare the cost of being in the wrong state >> to the cost of the OR gate, is it all that bad? (snip) >> And if an alpha particle comes through and it does get into the wrong >> state then you are stuck. > Because that wide wide NOR gate is _expensive_. As I said, it depends on the cost of being in the wrong state. If it is part of a car engine control system (no suggestion that anyone does that) then the cost could be high. If you mean expensive in critical path, then pipeline it. That delays the number of cycles to get out of the bad state, but much of the time you can live with that. Many FPGA designs aren't so full that the extra logic would be that bad. Not enough to be 'clearly bad' to me. -- glen
From: Tim Wescott on 4 Feb 2010 21:10 On Fri, 05 Feb 2010 01:31:02 +0000, glen herrmannsfeldt wrote: > Tim Wescott <tim(a)seemywebsite.com> wrote: >> On Thu, 04 Feb 2010 23:05:18 +0000, glen herrmannsfeldt wrote: >>> Al Clark <aclark(a)danvillesignal.com> wrote: (snip) > >>>> You could use an N input NOR connected to each output state. The >>>> output of the NOR would be 0 for all situations except the all 0 >>>> state. > (snip) > >>>> This is clearly a very bad solution. > >>> Why is it so bad? If you compare the cost of being in the wrong state >>> to the cost of the OR gate, is it all that bad? > (snip) > >>> And if an alpha particle comes through and it does get into the wrong >>> state then you are stuck. > >> Because that wide wide NOR gate is _expensive_. > > As I said, it depends on the cost of being in the wrong state. If it is > part of a car engine control system (no suggestion that anyone does > that) then the cost could be high. > > If you mean expensive in critical path, then pipeline it. That delays > the number of cycles to get out of the bad state, but much of the time > you can live with that. > > Many FPGA designs aren't so full that the extra logic would be that bad. > Not enough to be 'clearly bad' to me. > > -- glen Or 'clearly very bad'. It is a whole lot more gates than a plain ol' LFSR -- see my counter idea for something that is (probably) fewer gates, and works (probably) similar to your pipelined idea. -- www.wescottdesign.com
From: Vladimir Vassilevsky on 4 Feb 2010 21:11
glen herrmannsfeldt wrote: >>>And if an alpha particle comes through and it does get into the wrong >>>state then you are stuck. > > As I said, it depends on the cost of being in the wrong state. > If it is part of a car engine control system (no suggestion that > anyone does that) then the cost could be high. > > If you mean expensive in critical path, then pipeline it. > That delays the number of cycles to get out of the bad state, > but much of the time you can live with that. > > Many FPGA designs aren't so full that the extra logic would be > that bad. Not enough to be 'clearly bad' to me. Military grade encryption hardware runs self checks at every cycle. The amount of circutry related to that is much higher then required by the basic functionality. And then there is always a problem of who is going to guard the guards. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com |