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From: glen herrmannsfeldt on 4 Feb 2010 22:01 robert bristow-johnson <rbj(a)audioimagination.com> wrote: (snip) > no, it wasn't that, Jerry. 0xFFFF becomes 0x7FFF. > it was weird. > assuming right-shifting, it had to be an even number. it would get > right-shifted, XORed and afterward it would be the same number. If the state register is x, and the XOR value is a, then (x>>1)^a==x, or in verilog form x[n-1:1]^a[n-2:0]==x[n-2:0] x[0]==0 (the condition for the XOR). I think a[n-1] has to be 1, otherwise it is an n-1 bit LFSR. x[1]^a[0]=x[0]=0 x[1]=a[0] x[2]^a[1]=x[1]=a[0] x[2]=a[0]^a[1] x[3]^a[2]=x[2]= x[3]=a[0]^a[1]^a[2] etc. -- glen
From: robert bristow-johnson on 4 Feb 2010 22:25 On Feb 4, 10:01 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > robert bristow-johnson <r...(a)audioimagination.com> wrote: > > (snip) > > > no, it wasn't that, Jerry. 0xFFFF becomes 0x7FFF. > > it was weird. > > assuming right-shifting, it had to be an even number. it would get > > right-shifted, XORed and afterward it would be the same number. > > If the state register is x, and the XOR value is a, > then (x>>1)^a==x, or in verilog form > > x[n-1:1]^a[n-2:0]==x[n-2:0] > x[0]==0 (the condition for the XOR). > I think a[n-1] has to be 1, otherwise it is an n-1 bit LFSR. yes, same as with the top n bits of an nth-order primitive polynomial (which is i think what i used. > x[1]^a[0]=x[0]=0 x[1]=a[0] > x[2]^a[1]=x[1]=a[0] x[2]=a[0]^a[1] > x[3]^a[2]=x[2]= x[3]=a[0]^a[1]^a[2] well, somebuddy other than me (maybe the OP) gets to check this out. i don't have time, but i think it works. the issue is, just like a regular MLS, there is a state that, if you somehow find yourself in that state (like if the alpha particle comes in and flips a bit) you're stuck in it (until the next alpha particle comes along and knocks you out of it). but you could start with a cleared register and go through all other states, and i'll bet if you picked out a single bit out, it would qualify as an MLS of sorts (psuedo-white noise). r b-j
From: robert bristow-johnson on 4 Feb 2010 22:30 On Feb 4, 9:42 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > Tim Wescott <t...(a)seemywebsite.com> wrote: > > (big snip regarding LFSR, the stationary state, and how to get > out of it.) > > > Or 'clearly very bad'. > > It is a whole lot more gates than a plain ol' LFSR -- see my counter idea > > for something that is (probably) fewer gates, and works (probably) > > similar to your pipelined idea. > > Now I wonder how many zeros in a row can be generated by an N bit LFSR. why wouldn't that be N-1? r b-j
From: Jerry Avins on 4 Feb 2010 23:22 glen herrmannsfeldt wrote: > Tim Wescott <tim(a)seemywebsite.com> wrote: > (big snip regarding LFSR, the stationary state, and how to get > out of it.) > >> Or 'clearly very bad'. > >> It is a whole lot more gates than a plain ol' LFSR -- see my counter idea >> for something that is (probably) fewer gates, and works (probably) >> similar to your pipelined idea. > > Now I wonder how many zeros in a row can be generated by an N bit LFSR. > > -- glen n-1? Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
From: Al Clark on 4 Feb 2010 23:35
Tim Wescott <tim(a)seemywebsite.com> wrote in news:dKydnam7PZFR8vbWnZ2dnUVZ_gZi4p2d(a)web-ster.com: > On Thu, 04 Feb 2010 23:05:18 +0000, glen herrmannsfeldt wrote: > >> Al Clark <aclark(a)danvillesignal.com> wrote: (snip) >> >>> You could use an N input NOR connected to each output state. The output >>> of the NOR would be 0 for all situations except the all 0 state. You >>> could take this value and OR with any one of the output states. This >>> would cause an all 0 condition to be changed to one with a single 1 >>> state. At this point the states would change to the 2n-1 sequence. Once >>> in a 2n-1 sequence, the OR function would never cause a change in the >>> next state since you would always be ORing a 0. >> >>> This is clearly a very bad solution. >> >> Why is it so bad? If you compare the cost of being in the wrong state >> to the cost of the OR gate, is it all that bad? >> >>> In software, you just initialize a seed to be non zero. >> >>> In hardware, the VLV solution adds an inverter to the output >>> of a flip flop. If you then perform a RESET, you have a >>> seed with a single 1, which will avoid the all zero state. >> >> And if an alpha particle comes through and it does get into the wrong >> state then you are stuck. >> >> -- glen > Because that wide wide NOR gate is _expensive_. > Exactly. I only suggested it as a method that eliminates the zero state. As an engineer, I think it is overly complicated. The inverter method is probably much better since a stray reset will still cause the sequence to go back to a long sequence. If the sequence is reasonably long, the alpha particle will need to be very lucky to cause the all zero state. I think the probabity of circuit failure is much much higher. Al |