Prev: FPGA on-die LVDS termination issues
Next: Gen3 SATA 6.0Gbps HDD simulation model
From: subagha on 13 Oct 2009 08:16
Hi,
I have a small design in VHDL with black box which i am trying to
synthesize
using Xilinx ISE 11.2.

I get an error when running the command ngdbuild.
ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not
be
resolved. A pin name misspelling can cause this, a missing edif or ngc
file,
or the misspelling of a type name. Symbol 'my_block' is not supported
in
target 'virtex5'.


The design has two files

my_block.vhd ---
library ieee;
use ieee.std_logic_1164.all;

entity my_block is
port(I1, I2 : in std_logic;
O : out std_logic);
end my_block;

architecture tmp of my_block is

begin

end tmp;


black_box_1.vhd ---

library ieee;
use ieee.std_logic_1164.all;

entity black_box_1 is
port(DI_1, DI_2 : in std_logic;
DOUT : out std_logic);
end black_box_1;

architecture archi of black_box_1 is

component my_block
port (I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE: string;
attribute BOX_TYPE of my_block: component is "BLACK_BOX";

begin

inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);

end archi;

I am using the commandline to run my commands and not the GUI.

command which generated error:
ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759
black_box_1.ngc black_box_1.ngd

I am a newbie to XST. So your help is most appreciated. Please explain
all the steps i need to do as i am a newbie to XST.I normally use
command line to run the tools so please send across a solution for
command line.

Thanking you in advance

regards,
suba



From: Alan Fitch on 13 Oct 2009 08:56
subagha wrote:
> Hi,
> I have a small design in VHDL with black box which i am trying to
> synthesize
> using Xilinx ISE 11.2.
>
> I get an error when running the command ngdbuild.
> ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not
> be
> resolved. A pin name misspelling can cause this, a missing edif or ngc
> file,
> or the misspelling of a type name. Symbol 'my_block' is not supported
> in
> target 'virtex5'.
>
>
> The design has two files
>
> my_block.vhd ---
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity my_block is
> port(I1, I2 : in std_logic;
> O : out std_logic);
> end my_block;
>
> architecture tmp of my_block is
>
> begin
>
> end tmp;
>
>
> black_box_1.vhd ---
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity black_box_1 is
> port(DI_1, DI_2 : in std_logic;
> DOUT : out std_logic);
> end black_box_1;
>
> architecture archi of black_box_1 is
>
> component my_block
> port (I1 : in std_logic;
> I2 : in std_logic;
> O : out std_logic);
> end component;
> attribute BOX_TYPE: string;
> attribute BOX_TYPE of my_block: component is "BLACK_BOX";
>
> begin
>
> inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);
>
> end archi;
>
> I am using the commandline to run my commands and not the GUI.
>
> command which generated error:
> ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759
> black_box_1.ngc black_box_1.ngd
>
> I am a newbie to XST. So your help is most appreciated. Please explain
> all the steps i need to do as i am a newbie to XST.I normally use
> command line to run the tools so please send across a solution for
> command line.
>
> Thanking you in advance
>
> regards,
> suba
>
>
>

Hi Suba,

you're not just synthesizing, you're doing place and route as well. The
place and route fails because it cannot find a file my_block.ngd.

You can't have a black box at place and route, only during synthesis.

regards
Alan



--
Alan Fitch
Senior Consultant

Doulos � Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch(a)doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

------------------------------------------------------------------------

This message may contain personal views which are not the views of
Doulos, unless specifically stated.
From: Brian Drummond on 13 Oct 2009 19:25
On Tue, 13 Oct 2009 07:16:06 -0500, "subagha" <subagha(a)gmail.com> wrote:

>Hi,
> I have a small design in VHDL with black box which i am trying to
>synthesize
>using Xilinx ISE 11.2.
>
>I get an error when running the command ngdbuild.
>ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not
>be
> resolved. A pin name misspelling can cause this,

>>> a missing edif or ngc file,

>The design has two files
>
>my_block.vhd ---

>black_box_1.vhd ---

>I am using the commandline to run my commands and not the GUI.

Have you run synthesis, with the correct settings, on my_block.vhd?
You need to synthesise this WITHOUT inserting I/O buffers on its ports, to
generate my_block.ngc.

If you can't find the correct commandline options, use the GUI to synth without
IOB insertion, and copy the command line from the .commandlog file into your
scripts.

>command which generated error:
>ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759
>black_box_1.ngc black_box_1.ngd

And as the error message says, it can't find my_block.ngc.

If my_block.ngc existed, ngdbuild would use it to fill in the black box.
(This is how an EDK project is incorporated into to an ISE flow)

If my_block.ngc exists but ngdbuild can't find it, it may be in the wrong
directory. You can keep all your black box .ngc files in a separate folder and
use a command line option to tell ngdbuild to look there for them.

- Brian

 | 
Pages: 1
Prev: FPGA on-die LVDS termination issues
Next: Gen3 SATA 6.0Gbps HDD simulation model