Problems in simulation (Webpack 9.1.03i)
in [FPGA]
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From: Thomas Heller on 18 Apr 2007 13:40 Finally I got simulation of logicores in webpack 9.1.03i to work with the ISE simulator. However, these messages appear in the transcript window: Running Fuse ... WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. Entity <detector> compiled. Entity <detector> (Architecture <behavioral>) compiled. WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" first. WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector_tbw.vhw" in Library work. Entity <detector_tbw> compiled. Entity <detector_tbw> (Architecture <testbench_arch>) compiled. Parsing "detector_tbw_beh.prj": 1.84 Codegen work/detector: 0.00 Codegen work/detector/Behavioral: 0.41 Codegen work/detector_tbw: 0.00 Codegen work/detector_tbw/testbench_arch: 0.34 Building detector_tbw_isim_beh.exe Running ISim simulation engine ... This is a Lite version of ISE Simulator. Simulator is doing circuit initialization process. Finished circuit initialization process. Apparently this file "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" isn't present on my system, it is probably a filename in Xilinx source code. How can I recompile this file??? Other files like these "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" *are* present on my system, but *I* did not change them. How can it be that they need to be compiled? How would I compile them? Do I have a broken installation? Or should I not be bothered at all by these messages? Thanks for any help, Thomas
From: Duth on 19 Apr 2007 10:32 On Apr 18, 11:40 am, Thomas Heller <thel...(a)python.net> wrote: > Finally I gotsimulationof logicores in webpack 9.1.03i to work with the ISE simulator. > However, these messages appear in the transcript window: > > Running Fuse ... > WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. > Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. > Entity <detector> compiled. > Entity <detector> (Architecture <behavioral>) compiled. > WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. > WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. > WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" first. > WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. > Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector_tbw.vhw" in Library work. > Entity <detector_tbw> compiled. > Entity <detector_tbw> (Architecture <testbench_arch>) compiled. > Parsing "detector_tbw_beh.prj": 1.84 > Codegen work/detector: 0.00 > Codegen work/detector/Behavioral: 0.41 > Codegen work/detector_tbw: 0.00 > Codegen work/detector_tbw/testbench_arch: 0.34 > Building detector_tbw_isim_beh.exe > Running ISimsimulationengine ... > This is a Lite version of ISE Simulator. > Simulator is doing circuit initialization process. > Finished circuit initialization process. > > Apparently this file "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" isn't present on my system, it is probably a filename inXilinxsource code. How can I recompile this file??? > > Other files like these > "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" > "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" > "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" > *are* present on my system, but *I* did not change them. > > How can it be that they need to be compiled? How would I compile them? > Do I have a broken installation? > Or should I not be bothered at all by these messages? > > Thanks for any help, > Thomas Hi Thomas, Can you try to do a clean up project files and ensure that you have both: - Latest Service Pack - Latest IP Update The order in which you install should be the order in which it was released. If you use webupdate, then this will take care of this for you. Sounds like it is trying to look an older compiler version somewhere and that is why you are getting the error. Thanks Duth
From: Thomas Heller on 19 Apr 2007 15:54 Duth schrieb: > On Apr 18, 11:40 am, Thomas Heller <thel...(a)python.net> wrote: >> Finally I gotsimulationof logicores in webpack 9.1.03i to work with the ISE simulator. >> However, these messages appear in the transcript window: >> >> Running Fuse ... >> WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. >> Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. [...] >> Thanks for any help, >> Thomas > > Hi Thomas, > > Can you try to do a clean up project files and ensure that you have > both: > > - Latest Service Pack > - Latest IP Update > > The order in which you install should be the order in which it was > released. If you use webupdate, then this will take care of this for > you. Sounds like it is trying to look an older compiler version > somewhere and that is why you are getting the error. Ah, cool. Webupdate reported 'no updates to display', but 'Cleanup Project Files' made the warnings go away. Many thanks for the help, Thomas
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