Prev: Controlling Path Delay with Constraints?
Next: Discount dc hats and caps ( www.nike-black.com )
From: salimbaba on 8 Jul 2010 11:03
is it possible to program only one FPGA in the chain from EEPROM i.e. first
FPGA without disconnecting other one from the loop.?

Also, how do we generate the mcs file for the daisy chained FPGAs?

Thanks

---------------------------------------
Posted through http://www.FPGARelated.com
From: d_s_klein on 8 Jul 2010 13:35
On Jul 8, 8:03 am, "salimbaba"
<a1234573(a)n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

> is it possible to program only one FPGA in the chain from EEPROM i.e. first
> FPGA without disconnecting other one from the loop.?

Yes. The difficulty is getting just one FPGA in a chain into program
mode.

> Also, how do we generate the mcs file for the daisy chained FPGAs?

Xilinx Impact. There's an XAPP for that.

> Thanks    

Ciao.
From: salimbaba on 8 Jul 2010 14:57
Can u give me a link to the xapp ?

---------------------------------------
Posted through http://www.FPGARelated.com
From: d_s_klein on 9 Jul 2010 01:16
On Jul 8, 11:57 am, "salimbaba"
<a1234573(a)n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Can u give me a link to the xapp ?        
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

<http://www.google.com/search?q=UG332> Same book symon pointed you
to.

The restriction is that it is only the 1st chip can be done by
itself. (If you can get around the other problem I mentioned.)

How to create an mcs file is here:
<http://www.google.com/search?q=impact+user+guide>

Cheers!
From: rickman on 9 Jul 2010 11:56
On Jul 9, 1:16 am, d_s_klein <d_s_kl...(a)yahoo.com> wrote:
> On Jul 8, 11:57 am, "salimbaba"
>
> <a1234573(a)n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> > Can u give me a link to the xapp ?        
>
> > ---------------------------------------        
> > Posted throughhttp://www.FPGARelated.com
>
> <http://www.google.com/search?q=UG332>  Same book symon pointed you
> to.
>
> The restriction is that it is only the 1st chip can be done by
> itself.  (If you can get around the other problem I mentioned.)
>
> How to create an mcs file is here:
> <http://www.google.com/search?q=impact+user+guide>
>
> Cheers!

Is that true? If the PROG signals to each FPGA are separate, then any
of the chips can be put into programming mode. When being configured,
once an FPGA has received its entire bitstream and is ready to enter
user mode, it passes all configuration data received out to the next
chip which does the same. I don't know if the FPGAs continue to pass
the configuration data after they have transitioned into user mode,
but if they do, you should be able to put one chip into configuration
mode and pass the bitstream through the other FPGAs.

Does anyone know if these FPGAs continue to pass configuration data
after they enter user mode?

Rick
 |  Next  |  Last
Pages: 1 2
Prev: Controlling Path Delay with Constraints?
Next: Discount dc hats and caps ( www.nike-black.com )