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From: Andreas Ehliar on 6 Sep 2006 07:33
I'm playing around a bit with RLOC and I'm getting some weird
results.

My top level file has these instantiations in it:

(* RLOC = "X0Y0" *) rloc_reg32 sourcefds(.clk_i(clk_i),.D(internal2),.Q(thebus));
(* RLOC = "X60Y0" *) rloc_reg32 destfds(.clk_i(clk_i),.D(thebus),.Q(internal4));

And rloc_reg32 looks like this:

module rloc_reg32(input clk_i,
input [31:0] D,
output [31:0] Q);
(* RLOC = "X0Y0" *) FD fd00(.C(clk_i),.D(D[ 0]),.Q(Q[ 0]));
(* RLOC = "X0Y0" *) FD fd01(.C(clk_i),.D(D[ 1]),.Q(Q[ 1]));
(* RLOC = "X2Y0" *) FD fd02(.C(clk_i),.D(D[ 2]),.Q(Q[ 2]));
(* RLOC = "X2Y0" *) FD fd03(.C(clk_i),.D(D[ 3]),.Q(Q[ 3]));
(* RLOC = "X0Y2" *) FD fd04(.C(clk_i),.D(D[ 4]),.Q(Q[ 4]));
(* RLOC = "X0Y2" *) FD fd05(.C(clk_i),.D(D[ 5]),.Q(Q[ 5]));
(* RLOC = "X2Y2" *) FD fd06(.C(clk_i),.D(D[ 6]),.Q(Q[ 6]));
(* RLOC = "X2Y2" *) FD fd07(.C(clk_i),.D(D[ 7]),.Q(Q[ 7]));
(* RLOC = "X0Y4" *) FD fd08(.C(clk_i),.D(D[ 8]),.Q(Q[ 8]));
(* RLOC = "X0Y4" *) FD fd09(.C(clk_i),.D(D[ 9]),.Q(Q[ 9]));
// And so on...
(* RLOC = "X0Y14" *) FD fd28(.C(clk_i),.D(D[28]),.Q(Q[28]));
(* RLOC = "X0Y14" *) FD fd29(.C(clk_i),.D(D[29]),.Q(Q[29]));
(* RLOC = "X2Y14" *) FD fd30(.C(clk_i),.D(D[30]),.Q(Q[30]));
(* RLOC = "X2Y14" *) FD fd31(.C(clk_i),.D(D[31]),.Q(Q[31]));
endmodule // rloc_reg32


Basically, I expect that I should be able to get two columns
of CLBs with each CLB containing two flip flops.

However, if I look at the design the flip flops in "destfds"
are not placed as I expect them to be. I have a screenshot
of the placed design at http://www.da.isy.liu.se/~ehliar/priv/rloc.png .
As you can see, the rloc_reg32 instance in the right has one CLB
between the columns of flip flops whereas the instance to the left
has no CLB between the columns of flip flops.

Have I misunderstood something about RLOC? I have tried to search the
answer database at xilinx.com but haven't found anything which
explains this. (I'm using ISE 8.1 if that matters.)

/Andreas
From: Andreas Ehliar on 6 Sep 2006 07:58
On 2006-09-06, Andreas Ehliar <ehliar(a)lysator.liu.se> wrote:
> However, if I look at the design the flip flops in "destfds"
> are not placed as I expect them to be. I have a screenshot
> of the placed design at http://www.da.isy.liu.se/~ehliar/priv/rloc.png .
> As you can see, the rloc_reg32 instance in the right has one CLB
> between the columns of flip flops whereas the instance to the left
> has no CLB between the columns of flip flops.

I now noticed that I got the following error when opening the design
in the FPGA editor:

ERROR:Place:346 - The components related to The RPM "hset" can not be placed in the required relative placement form

The following components are part of this structure:
SLICEL thebus<1>, placed to site SLICE_X4Y92
SLICEL thebus<5>, placed to site SLICE_X4Y94
SLICEL thebus<9>, placed to site SLICE_X4Y96
SLICEL thebus<13>, placed to site SLICE_X4Y98
SLICEL thebus<17>, placed to site SLICE_X4Y100
SLICEL thebus<3>, placed to site SLICE_X6Y92
SLICEL thebus<7>, placed to site SLICE_X6Y94
SLICEL thebus<11>, placed to site SLICE_X6Y96
SLICEL thebus<15>, placed to site SLICE_X6Y98
SLICEL thebus<19>, placed to site SLICE_X6Y100
SLICEL internal4<1>, placed to site SLICE_X72Y92
SLICEL internal4<5>, placed to site SLICE_X72Y94
SLICEL internal4<9>, placed to site SLICE_X72Y96
SLICEL internal4<13>, placed to site SLICE_X72Y98
SLICEL internal4<17>, placed to site SLICE_X72Y100
SLICEL internal4<3>, placed to site SLICE_X76Y92
SLICEL internal4<7>, placed to site SLICE_X76Y94
SLICEL internal4<11>, placed to site SLICE_X76Y96
SLICEL internal4<15>, placed to site SLICE_X76Y98
SLICEL internal4<19>, placed to site SLICE_X76Y100
SLICEL thebus<21>, placed to site SLICE_X4Y102
SLICEL thebus<25>, placed to site SLICE_X4Y104
SLICEL thebus<29>, placed to site SLICE_X4Y106
SLICEL thebus<23>, placed to site SLICE_X6Y102
SLICEL thebus<27>, placed to site SLICE_X6Y104
SLICEL thebus<31>, placed to site SLICE_X6Y106
SLICEL internal4<21>, placed to site SLICE_X72Y102
SLICEL internal4<25>, placed to site SLICE_X72Y104
SLICEL internal4<29>, placed to site SLICE_X72Y106
SLICEL internal4<23>, placed to site SLICE_X76Y102
SLICEL internal4<27>, placed to site SLICE_X76Y104
SLICEL internal4<31>, placed to site SLICE_X76Y106

The reason for this issue is the following:
All of the logic associated with this structure is already placed and the relative placement of the logic violates the structure. The problem was found between the relative placement of SLICEL thebus<19> at site SLICE_X6Y100 and SLICEL internal4<1> at site SLICE_X72Y92.


Changing the RLOC constraint to X72Y0 instead of X70Y0 in the top level
file seems to have corrected the problem. However I am kind of irritated
that I didn't seem to get any error or warning message about this
during place & route...


/Andreas
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