ROM wait states
in [Embedded]
|
Prev: Please tell me what is the cheapest ARM with my request ip(100K annual)
Next: Use of MAX232 as power supply for operational amplifier in 5V powered system?
From: RIYA on 11 Oct 2009 09:41 can anyone explain me to calculate the wait states needed? Suppose we are using 120 nanosecond ROMs, which have valid data on the bus 120 ns after the falling edge on the Output Enable line with a clock rate of 25 MHz (which means a clock cycle of 40 nanoseconds). How many wait states must the microprocessor insert into each bus cycle that reads from the ROM? --------------------------------------- This message was sent using the comp.arch.embedded web interface on http://www.EmbeddedRelated.com
From: Frank Buss on 11 Oct 2009 09:55 RIYA wrote: > can anyone explain me to calculate the wait states needed? > Suppose we are using 120 nanosecond ROMs, which have valid data on the bus > 120 ns after the falling edge on the Output Enable line with a clock rate > of 25 MHz (which means a clock cycle of 40 nanoseconds). How many wait > states must the microprocessor insert into each bus cycle that reads from > the ROM? Maybe 3 wait states? But you have to check the timing diagrams of the datasheets of the ROM and the microprocessor. "wait state" doesn't mean always the same and there could be other timing constants, e.g. how long the ROM needs to release the address bus after chip select release. Draw a timing diagrams on a big paper for your system and verify it with the datasheets. If you want to document it, this is a nice font for it: http://www.pcserviceselectronics.co.uk/fonts/ -- Frank Buss, fb(a)frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
From: -jg on 11 Oct 2009 22:05
On Oct 12, 2:41 am, "RIYA" <RIYAGIY...(a)GMAIL.COM> wrote: > can anyone explain me to calculate the wait states needed? > Suppose we are using 120 nanosecond ROMs, which have valid data on the bus > 120 ns after the falling edge on the Output Enable line with a clock rate > of 25 MHz (which means a clock cycle of 40 nanoseconds). How many wait > states must the microprocessor insert into each bus cycle that reads from > the ROM? Homework ? - the Output enable time is not the only access time you need. Ask your tutor what the Address access time is, on these mythical '120ns ROMs' A wait state equation also do not tend to start from zero.(ie pass thru a virtual origin), so you need two numbers to calculate a wait state. -jg |