RS-Latch
in [FPGA]
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From: firefox3107 on 27 Jul 2010 14:41 Hey, I have to implement a RS-Latch. I know that it is not a good design practice but because of limited clocks, I have to use it. Now my concerns are that this latch could go metastable. In my design, the reset and set input of the latch are not set simultaneously. But before the set input there is a AND gate which is fed by asynchronous inputs. Thus it is possible that the set input of the RS-Latch is set by a runt pulse or anything between '0' and '1'. So, my question is, if my concerns are legitimated?
From: Gabor on 27 Jul 2010 17:57 On Jul 27, 2:41 pm, firefox3107 <firefox3...(a)gmail.com> wrote: > Hey, > > I have to implement a RS-Latch. I know that it is not a good design > practice but because of limited clocks, I have to use it. > Now my concerns are that this latch could go metastable. In my design, > the reset and set input of the latch are not set simultaneously. But > before the set input there is a AND gate which is fed by asynchronous > inputs. Thus it is possible that the set input of the RS-Latch is set > by a runt pulse or anything between '0' and '1'. > > So, my question is, if my concerns are legitimated? What sort of device is this going into? In the older Xilinx families RS latches are simply made with D flip-flops using both asynchronous set and reset. Newer devices only have a choice of either set or reset and therefore cause the latch to be built some other way, which will not have as good timing. As to the AND gate, unless the device is broken, there should be no runt pulses unless there is an actual overlap time when all inputs are high (as seen at the gate inputs, which may be after significant routing delays). Inside the FPGA, signals don't spend much time "between '0' and '1'", so I don't see where you're going with that... Regards, Gabor
From: KJ on 27 Jul 2010 18:55 On Jul 27, 2:41 pm, firefox3107 <firefox3...(a)gmail.com> wrote: > Hey, > > I have to implement a RS-Latch. I know that it is not a good design > practice but because of limited clocks, I have to use it. The 'limited clocks' statement doesn't make much sense. The only reason to not use a flop in this instance is if the time that the 'R' or the 'S' is active is less than the period of whatever clock(s) you might have. Is that really the case? Is there really nothing you can do to extend the length of time that 'R' or 'S' are active so that they are guaranteed to be at least one clock cycle wide? > Now my concerns are that this latch could go metastable. In my design, > the reset and set input of the latch are not set simultaneously. But > before the set input there is a AND gate which is fed by asynchronous > inputs. Thus it is possible that the set input of the RS-Latch is set > by a runt pulse or anything between '0' and '1'. > > So, my question is, if my concerns are legitimated? Probably...maybe not necessarily metastability, but also consider race conditions in which the 'R' or 'S' gets set momentarily because of the async logic that generates 'R' and 'S'. Asynchronous logic feeding sets/resets/clocks in FPGAs can be dicey if not done properly and is always something to: - Look at very closely to see if there is a synchronous way to do it instead - Look at the timing analysys very closely...it is very easy to be misled here also which leads to thinking that you're right when you're really wrong. Kevin Jennings
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