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From: Ulf Samuelsson on 9 Sep 2006 13:39
"rickman" <gnuarm(a)gmail.com> skrev i meddelandet
news:1157546456.490519.80300(a)m79g2000cwm.googlegroups.com...
> Alf Katz wrote:
>> "rickman" <gnuarm(a)gmail.com> wrote in message
>> news:1157507358.338962.101330(a)m79g2000cwm.googlegroups.com...
>> >
>> > Yes, sorry I forgot the question. I am looking for timing specs on the
>> > bus.
>> >
>>
>> Yepp, as you've alluded to elsewhere, there is no timing spec for the
>> bus.
>> This is determined entirely by the devices at either end. Some devices
>> can
>> only run at 100kbaud or so, while others run at faster than 80Mbaud.
>> Asking
>> for a generic timing spec is a bit like asking for a single timing spec
>> for
>> microprocessor parallel busses.
>
> I am getting that. Unlike nearly all other serial buses, SPI has no
> real spec and, as you say, is like embedded CPU memory busses, a custom
> design for each device. That is a good analogy. But even CPU memory
> busses have become standardized to work with standard memory such as
> SDRAM, DDR, etc.
>

No, you have to do a timing analyzis of the combination of CPU and Memory
to find out how many waitstates you need.
You also need to check if you violate setup and hold times.

This is exactly the same with the SPI bus.
It defines four different modes, which are explained in most decent chapters
in microcontrollers, but the setup and hold times are device dependent.

--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB





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