SPI Bus Specification
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From: rickman on 5 Sep 2006 12:51 I searched this group and could not find much on an actual spec for the SPI bus. I know that this bus is very loose. One of my coworkers refers to it as a non-standard standard. But I will be doing some strange things to a couple of SPI bus interfaces to pass them through a cable using fewer pins than otherwise required and the relative timing will be delayed by up to a uS or so. The bus will be running with a 101 kHz clock so I expect this will work, but I wanted to find some timing data on the bus. I did find a Freescale doc that shows the clock phasing an polarity, but no timing requirements. I guess it is up to the engineer to verify the low level timing of the various devices on the bus? I could not find anything on timing at the Freescale site.
From: Jim Stewart on 5 Sep 2006 13:17 rickman wrote: > I searched this group and could not find much on an actual spec for the > SPI bus. I know that this bus is very loose. One of my coworkers > refers to it as a non-standard standard. But I will be doing some > strange things to a couple of SPI bus interfaces to pass them through a > cable using fewer pins than otherwise required and the relative timing > will be delayed by up to a uS or so. The bus will be running with a > 101 kHz clock so I expect this will work, but I wanted to find some > timing data on the bus. > > I did find a Freescale doc that shows the clock phasing an polarity, > but no timing requirements. I guess it is up to the engineer to verify > the low level timing of the various devices on the bus? > > I could not find anything on timing at the Freescale site. You never really asked a question so I'm not sure whether you're interested in a reply. In any case, I've had much the same experience. There doen't seem to be anything like a formal published specification. I've had to analyze each implementation I've done.
From: Noway2 on 5 Sep 2006 13:22 rickman wrote: > I searched this group and could not find much on an actual spec for the > SPI bus. I know that this bus is very loose. One of my coworkers > refers to it as a non-standard standard. But I will be doing some > strange things to a couple of SPI bus interfaces to pass them through a > cable using fewer pins than otherwise required and the relative timing > will be delayed by up to a uS or so. The bus will be running with a > 101 kHz clock so I expect this will work, but I wanted to find some > timing data on the bus. > > I did find a Freescale doc that shows the clock phasing an polarity, > but no timing requirements. I guess it is up to the engineer to verify > the low level timing of the various devices on the bus? > > I could not find anything on timing at the Freescale site. You are probably more likely to run into a setup or hold timing violation with the particular logic devices you are using, as opposed to an overall SPI timing specification issue. Even though you are running at 101KHz, clock rate, you could still run into timing troubles relative to the data to clock timing.
From: Jim Granville on 5 Sep 2006 16:11 rickman wrote: > I searched this group and could not find much on an actual spec for the > SPI bus. I know that this bus is very loose. One of my coworkers > refers to it as a non-standard standard. But I will be doing some > strange things to a couple of SPI bus interfaces to pass them through a > cable using fewer pins than otherwise required and the relative timing > will be delayed by up to a uS or so. The bus will be running with a > 101 kHz clock so I expect this will work, but I wanted to find some > timing data on the bus. > > I did find a Freescale doc that shows the clock phasing an polarity, > but no timing requirements. I guess it is up to the engineer to verify > the low level timing of the various devices on the bus? > > I could not find anything on timing at the Freescale site. Most data sheets I've seen spec this as one would a Serial shift register. So they have Clk-Data out, on one edge, and Tsu.Th times on the other edge. eg the AT89LP2052 data sheet has all this info ? Basically, from the time a clock edge and OP data appear, you have a nominal half-clock time MAX to get the IP data ready, or your SPI will notice your link. If you are pacing this, the other detail to watch, is to never change the relative skew delays : ie clock must appear before the DataOut, so that probably need special handling. -jg
From: Donald on 5 Sep 2006 19:50
Most chips that have an SPI port will define its version in their data sheet. This site is as generic as it can get. http://elm-chan.org/docs/spi_e.html |