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From: lecroy7200@chek.com on 22 Nov 2006 11:46
I tried the same tests setting the DCM to D=1 M=4, D=2 M=8 and setting
the CLKIN_DIVIDE_BY_2 to TRUE then using D=1 and M=8. All seem to
cause problems with the IDELAYCTRL.

I then took the RF generator (via the PECL driver) and used it to drive
the DCM.

Running the RF generator at 200MHz and using the CLK0 to drive the
IDELAYCTRL appears to work fine (delay per tap seems correct).

Running the RF generator at 50MHz and driving the DCM but using D=1 M=4
and the CLKFX out does not seem to work.

Running the RF generator at 100 MHz then using a D=1 M=2, CLKFX out
appears to work.

Running the RF generator at 200 MHz then using a D=2 M=2, CLKFX out
appears to work.

Austin had published a note about using a 66MHz clock with the DCM set
to D=1 M=3 and having it work.

"The Ref Clock may be supplied from any +/- 10% 200 MHz source,
including
the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3,
D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no
need
to be concerned with the jitter from the CLKFX, as the analog locked
loop which controls the delay is effectively a PLL which filters out
the
high frequency jitter components (jitter on Refclk is attenuated when
transfered to the data lines)."

I tried this same test and it appears not to work (I see that same
200pS / tap).

It seems to be related to how many multiplier stages used in the DCM.

Has anyone else seen this?

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