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From: Patrick Maupin on 8 Feb 2010 01:10
On Feb 7, 9:33 pm, Brian Davis <brimda...(a)aol.com> wrote:

> If you get anywhere with this, please post an update!

Well, I did a bit of work on how I could do a differential input amp,
and between the small signal I wanted to decode, the offset voltage I
was probably looking at with using discretes, and the fact I wanted to
have controlled hysteresis, I decided to go with an external
comparator. Microchip seems to have entered the market in a fairly
aggressive way; they hit the performance I need at a much better price
point than TI or Linear.

I could possibly use the internal receiver on the FPGA without an
external amplifier, but since Xilinx doesn't offer spice support and
the total market for this particular product probably isn't worth me
going in the lab and characterizing parts, I'm not going to do it.

On the one hand, I understand Xilinx's perspective, and at one level
it's a reasonable one -- they really only want to spend a lot on
supporting large customers doing fairly standard stuff. On the other
hand, when I go back and re-read a few of the threads here, they do
seem a bit gruff about it. For instance, when Steve Austin says that
the cost of HyperLynx is less than a single board spin, he's not
living in my world. On this project, I'm trying out various things on
a board I can plug into a S3A starter kit. Total cost of a spin is a
couple of hundred dollars, and lots of board rework can be tried
without actually doing a spin, and I don't anticipate any problems
that HyperLynx would actually solve for me in any case (especially
since I'm not a big customer that Xilinx would give an encrypted model
to).

Let me put it another way. You can't sell a single Spartan 3A for
$5.40 at DigiKey or Avnet Express and expect that everyone who buys a
single FPGA will have all the fancy tools, and that nobody who buys a
single FPGA will have silly questions. So, while I appreciate the
helpful information that Xilinx provides here, I also appreciate the
answers that I've seen you and Symon and rickman and countless others
give here over the years, and when I go back and read some of the
threads, it almost surprises me that some of you guys are still here
after some of the unwarranted flaming that you have received.

I've been using Xilinx parts for 13 years; been heavily involved in
projects which probably bought a total of over $2 million dollars of
parts from them, and a) I've never had to respin a board because of
any reason, much less SI (because I'm completely anal, and also
because I haven't done any really high-speed designs), and b) I've
never used anything remotely as complicated as HyperLynx. Steve acts
like it's plug and play, but I've looked at stuff like that, and
honestly, if you don't do it every day, the cost of ramping up to do
it is as bad as the non-trivial license cost.

So, although some of us would like to think that the whole purpose of
buying an FPGA is to remove as much other stuff from the board as
possible, I guess we have to add using any of the analog on the chip
in a non-standard way to the long list of things that Xilinx doesn't
want us to do. I just wish that we could convince them that it is
possible for them to document how things are implemented without them
having to support non-sanctioned use of the implementation. Sometimes
I think headway is being made (like with the USB cable drivers under
Linux), but sometimes it is very frustrating, especially when a
feature like the differential receiver looks like it might be able to
save me an external 60 cent part, but they don't think it's worthwhile
to give me the information that would allow me to make that
determination for myself.

Anyway, thanks for the information. I'm sure I will refer back to
this thread (and some of the previous threads) the next time I care
about detailed I/O pin characteristics.

Regards,
Pat
From: Patrick Maupin on 8 Feb 2010 01:10
On Feb 7, 9:33 pm, Brian Davis <brimda...(a)aol.com> wrote:

> If you get anywhere with this, please post an update!

Well, I did a bit of work on how I could do a differential input amp,
and between the small signal I wanted to decode, the offset voltage I
was probably looking at with using discretes, and the fact I wanted to
have controlled hysteresis, I decided to go with an external
comparator. Microchip seems to have entered the market in a fairly
aggressive way; they hit the performance I need at a much better price
point than TI or Linear.

I could possibly use the internal receiver on the FPGA without an
external amplifier, but since Xilinx doesn't offer spice support and
the total market for this particular product probably isn't worth me
going in the lab and characterizing parts, I'm not going to do it.

On the one hand, I understand Xilinx's perspective, and at one level
it's a reasonable one -- they really only want to spend a lot on
supporting large customers doing fairly standard stuff. On the other
hand, when I go back and re-read a few of the threads here, they do
seem a bit gruff about it. For instance, when Steve Austin says that
the cost of HyperLynx is less than a single board spin, he's not
living in my world. On this project, I'm trying out various things on
a board I can plug into a S3A starter kit. Total cost of a spin is a
couple of hundred dollars, and lots of board rework can be tried
without actually doing a spin, and I don't anticipate any problems
that HyperLynx would actually solve for me in any case (especially
since I'm not a big customer that Xilinx would give an encrypted model
to).

Let me put it another way. You can't sell a single Spartan 3A for
$5.40 at DigiKey or Avnet Express and expect that everyone who buys a
single FPGA will have all the fancy tools, and that nobody who buys a
single FPGA will have silly questions. So, while I appreciate the
helpful information that Xilinx provides here, I also appreciate the
answers that I've seen you and Symon and rickman and countless others
give here over the years, and when I go back and read some of the
threads, it almost surprises me that some of you guys are still here
after some of the unwarranted flaming that you have received.

I've been using Xilinx parts for 13 years; been heavily involved in
projects which probably bought a total of over $2 million dollars of
parts from them, and a) I've never had to respin a board because of
any reason, much less SI (because I'm completely anal, and also
because I haven't done any really high-speed designs), and b) I've
never used anything remotely as complicated as HyperLynx. Steve acts
like it's plug and play, but I've looked at stuff like that, and
honestly, if you don't do it every day, the cost of ramping up to do
it is as bad as the non-trivial license cost.

So, although some of us would like to think that the whole purpose of
buying an FPGA is to remove as much other stuff from the board as
possible, I guess we have to add using any of the analog on the chip
in a non-standard way to the long list of things that Xilinx doesn't
want us to do. I just wish that we could convince them that it is
possible for them to document how things are implemented without them
having to support non-sanctioned use of the implementation. Sometimes
I think headway is being made (like with the USB cable drivers under
Linux), but sometimes it is very frustrating, especially when a
feature like the differential receiver looks like it might be able to
save me an external 60 cent part, but they don't think it's worthwhile
to give me the information that would allow me to make that
determination for myself.

Anyway, thanks for the information. I'm sure I will refer back to
this thread (and some of the previous threads) the next time I care
about detailed I/O pin characteristics.

Regards,
Pat
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