Software PLL (SPLL)
in [DSP]
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From: kirgizz on 7 Feb 2006 09:27 Hello board, I'm dealing with synchronisation issue and looking for a cheap solution for my design. Firstly, my external reference frequency is variable and can change, for example, in sweep mode (5Hz per sec). Secondly, the exact information about the ext. reference frequency is used for internal calculations in DSP (to generate frequency-locked inphase and quadrature sine waves). That's why I'd like to implenent PLL in software (like 4046 series). I have an EZ-Kit lite DSP board from ADI with ADSP21262 onboard as basis (fclk=200Mhz). So I assume, it suits my design. more detailed: -reference signal in: TTL, 20Hz-20kHz -output signal: freq-locked sine waves -jitter (sync error): 0.01Hz (@20kHz) I read some ebooks about PLL so I understand (theoretically) its functionality. Furthermore I have implemented the loop filter and the NCO (in place of VCO). My problem is the phase detector PFD. How can I program a simple and precise lead-lag detector? In order to avoid additional hardware I'd rather use an ADC for sampling. As far as I know, timers from the ADSP21262 don't have suitable capture-mode for sampling purposes. Maybe someone have some good insights (more detailed)? Thank you in advance kirgizz
From: Noway2 on 7 Feb 2006 09:48 Thank you both. I think I understand things a bit better than before. I think the idea of using a gross zero crossing aproximator to drive the PLL into the neighborhood of the incoming frequency and then letting the loop filter / NCO take over sounds like a very workable idea. Tim, as I indicated, I have been planning this as a future sub project for a while now. I have played around with the PFD concept multiplying a reference and "line" (sine and cosine waves at various magnitudes, frequencies and phase offsets) and filtering the result in mathcad to get an intuitive feel for the operation and effects. From these experiments, I believe I understand what you are saying about the phase error I and Q rotating (like a vector spinning in time) and how depending on the phase relationship of the signals one will be high, the other will be low. The big part that I haven't addressed in time is the part about driving the NCO. I realize that the output of the loop filter does this, but I suspect part of the trick will be determining the gain or attenuation factor to the NCO, but that can wait till another day.
From: john on 7 Feb 2006 14:20 kirgizz wrote: > Hello board, > > I'm dealing with synchronisation issue and looking for a cheap solution > for my design. > > > Firstly, my external reference frequency is variable and can change, for > example, in sweep mode (5Hz per sec). Secondly, the exact information > about the ext. reference frequency is used for internal calculations in > DSP (to generate frequency-locked inphase and quadrature sine waves). > > That's why I'd like to implenent PLL in software (like 4046 series). > > I have an EZ-Kit lite DSP board from ADI with ADSP21262 onboard as basis > (fclk=200Mhz). So I assume, it suits my design. > > > more detailed: > -reference signal in: TTL, 20Hz-20kHz > -output signal: freq-locked sine waves > -jitter (sync error): 0.01Hz (@20kHz) > > I read some ebooks about PLL so I understand (theoretically) its > functionality. Furthermore I have implemented the loop filter and the NCO > (in place of VCO). > > My problem is the phase detector PFD. How can I program a simple and > precise lead-lag detector? In order to avoid additional hardware I'd > rather use an ADC for sampling. As far as I know, timers from the > ADSP21262 don't have suitable capture-mode for sampling purposes. > > > > Maybe someone have some good insights (more detailed)? > > > Thank you in advance > kirgizz Here is psuedo code for a lead-lag filter. It is simple. Its precision depends on the width of the accumulator, inputs, and outputs. If you have floating point then you're home free. coefs = [k1 k2] lead = x * k1 acc = acc + lead lag = acc * k2 y = lag + lead Good luck. John
From: kirgizz on 8 Feb 2006 05:45 > >John wrote: > >Here is psuedo code for a lead-lag filter. It is simple. Its precision >depends on the width of the accumulator, inputs, and outputs. If you >have floating point then you're home free. > >coefs = [k1 k2] >lead = x * k1 >acc = acc + lead >lag = acc * k2 >y = lag + lead > >Good luck. > >John > > Thank you John. A pair of thing here are not clear to me. What means x and why is y the sum of lag and lead? I thought expressions would looking like this: coefs = [k1 k2] lead = x * k1 lag = y * k2 acc = acc + lead - lag or coeff = kd acc = acc + lead - lag vd = kd*acc Have you programmed such software PLL? It's very interesting how do you get your x there? I mean the way you acquire the input square wave (by ADC or Timer). What did you use? regards, kirgizz
From: john on 8 Feb 2006 09:59 kirgizz wrote: > > > >John wrote: > > > >Here is psuedo code for a lead-lag filter. It is simple. Its precision > >depends on the width of the accumulator, inputs, and outputs. If you > >have floating point then you're home free. > > > >coefs = [k1 k2] > >lead = x * k1 > >acc = acc + lead > >lag = acc * k2 > >y = lag + lead > > > >Good luck. > > > >John > > > > > > Thank you John. > > A pair of thing here are not clear to me. > What means x and why is y the sum of lag and lead? > I thought expressions would looking like this: > > coefs = [k1 k2] > lead = x * k1 > lag = y * k2 > acc = acc + lead - lag > > or > > coeff = kd > acc = acc + lead - lag > vd = kd*acc > > Have you programmed such software PLL? It's very interesting how do you > get your x there? I mean the way you acquire the input square wave (by ADC > or Timer). What did you use? > > > > regards, > kirgizz Yes, I've programmed them. x is typically the phase error. It comes from a phase detector. There are quite a view different types. One is a zero crossing detector, in which the phase error is the value of high speed (compared to the input) counter at the time of the crossing. JS
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