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From: Andrew FPGA on 29 Mar 2010 21:37
Hi there,
Looking for insight here - Spartan 6 adds a PLL to the mix and we
wondered to what extent it can be used to filter jitter, for example
for a Synchronous Ethernet product requirement we have. However, the
SP6 PLL seems to have a very stringent max input jitter requirement.
It does not allow an input clock with more that 1ns jitter (not much).

Looking in the datasheet, the SP6 PLL looks like a classic PLL, so why
the input jitter requirement? (I can understand the jitter requriement
for a DCM).

I.e.
Table 49, pg 45 of DC and switching characteristics.
FINJITTER Maximum Input Clock Period Jitter All <20% of clock input
period or 1 ns Max

Anyone (from Xilinx?) prepared to comment on this?

Cheers
Andrew

From: austin on 30 Mar 2010 13:56
Andrew,

1ns is a LOT of jitter (in my book, that is). 20% of the clock period
is also a lot of jitter (to me).

Depends on what you define as "a lot."

Austin

From: Symon on 30 Mar 2010 14:03
On 3/30/2010 6:56 PM, austin wrote:
> Andrew,
>
> 1ns is a LOT of jitter (in my book, that is). 20% of the clock period
> is also a lot of jitter (to me).
>
> Depends on what you define as "a lot."
>
> Austin
>
Whether it is a lot or not depends on the frequency of the jitter. What
are we talking about here? Cycle-cycle jitter?

Syms.
From: austin on 30 Mar 2010 16:25
Good Question!

I am presuming it is peak to peak jitter, but I may be incorrect...

I will go ask.

Austin
From: austin on 30 Mar 2010 16:41
Peak to peak,

Austin
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