Termination of AC coupled 100MHz clok to generate low jitter 50MHz clock?
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From: John Larkin on 25 Jan 2010 14:53 On Mon, 25 Jan 2010 17:30:30 -0000, "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >> The LT1715 won't go faster than 150MHz > >Bill, > >Is this a problem if the input clock is 100MHz? > > > >> The Analog Devices AD96685 might be worth looking at, if you can live >> with ECL outputs. > >As usual my request wasn't fully spec'd. I'f prefer to power whatever I'm >using just 3.3V, I can provide 5V if I _have_ to. > > >> John Larkin's point about a tuned circuit in the front end is a good >> one. I once used a half-wavelength of delay line between the inverting >> and non-inverting inputs of a comparator to get a little more voltage >> drive, but three feet of even minature coax could be a bit too bulky >> for comfort. > >Space is fairly tight :-) > > >Thanks, > >Nial. > SN65LVDS2DBVR if you want CMOS output, FIN1101K8X if you'd like LVDS. Both are 3.3 volt; 58 and 85 cents respectively, faster than the LTC part which is $3.50 or so. John
From: Jim Thompson on 25 Jan 2010 16:29 On Mon, 25 Jan 2010 11:53:43 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Mon, 25 Jan 2010 17:30:30 -0000, "Nial Stewart" ><nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: > >>> The LT1715 won't go faster than 150MHz >> >>Bill, >> >>Is this a problem if the input clock is 100MHz? >> >> >> >>> The Analog Devices AD96685 might be worth looking at, if you can live >>> with ECL outputs. >> >>As usual my request wasn't fully spec'd. I'f prefer to power whatever I'm >>using just 3.3V, I can provide 5V if I _have_ to. >> >> >>> John Larkin's point about a tuned circuit in the front end is a good >>> one. I once used a half-wavelength of delay line between the inverting >>> and non-inverting inputs of a comparator to get a little more voltage >>> drive, but three feet of even minature coax could be a bit too bulky >>> for comfort. >> >>Space is fairly tight :-) >> >> >>Thanks, >> >>Nial. >> > >SN65LVDS2DBVR if you want CMOS output, FIN1101K8X if you'd like LVDS. > >Both are 3.3 volt; 58 and 85 cents respectively, faster than the LTC >part which is $3.50 or so. > >John > Don't you just love those Fairchild LVDS parts? You should... I was a major player in that design team in 2001 ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: John Larkin on 26 Jan 2010 00:47 On Mon, 25 Jan 2010 16:44:26 -0600, Tim Wescott <tim(a)seemywebsite.com> wrote: >On Mon, 25 Jan 2010 11:28:23 -0800, John Larkin wrote: > >> On Mon, 25 Jan 2010 12:13:56 -0600, Tim Wescott <tim(a)seemywebsite.com> >> wrote: >> >>>On Mon, 25 Jan 2010 07:03:24 -0800, John Larkin wrote: >>> >>>> On Mon, 25 Jan 2010 11:40:28 -0000, "Nial Stewart" >>>> <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >>>> >>>>>I have a requirement to terminate an AC coupled 100MHz clock and >>>>>produce an LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of >>>>>jitter isn't specified). >>>>> >>>>>The input is specified as an "AC coupled signal of 1mW into 50 ohms". >>>>> >>>>>I don't have any experience with low jitter clock distribution so am >>>>>unsure how to approach this. I currently have the clock terminated >>>>>then ac coupled and biased into a LT1715 (150MHz comparator) feeding a >>>>>single gate d type flip flop but am not confident this is the best >>>>>approach. >>>>> >>>>>Once you've all stopped rolling around laughing, I'd appreciate any >>>>>pointers to a better approach. >>>>> >>>>> >>>>>Thanks in advance, >>>>> >>>>> >>>>>Nial. >>>>> >>>>> >>>> That sounds reasonable. Expects low 10s of picoseconds RMS jitter, >>>> maybe below 10 if everything is perfect. Maybe worse if the signal is >>>> noisy. >>>> >>>> Adding a tuned circuit on the front end can help jitter performance a >>>> lot, by dumping ground loops, RF, any non-10-MHz stuff. If you design >>>> it to add a bit of voltage gain, even better. >>>> >>>> A faster comparator wouldn't hurt. LVDS line receivers make >>>> great:cheap fast comparators. >>>> >>>> John >>> >>>Note that if you're going into an impedance higher than 50 ohms that you >>>can get voltage gain from a resonant circuit. But if you design a >>>resonant circuit you either need some production guy to tune it or you >>>need to do some careful analysis to make sure that it works over >>>manufacturing variation and temperature. You'll definitely have a >>>tradeoff on the Q of the circuit -- higher Q means better noise >>>performance, but worse sensitivity to manufacturing gain. >> >> You can buy 2% surface-mount Rs and Cs these days, so something with a Q >> of three or so wouldn't be twitchey, and would jam a decent amount of >> swing into a comparator or LVDS receiver. Even at unity gain, a tuned >> circuit could help the jitter situation a lot. >> >> John > >Agreed. You may not have to think about it much, but you should still >think about it. Sure. Low jitter design isn't always obvious. Like here, too much Q might make things worse. John
From: Bill Sloman on 26 Jan 2010 10:26 On Jan 25, 6:30 pm, "Nial Stewart" <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote: > > The LT1715 won't go faster than 150MHz > > Bill, > > Is this a problem if the input clock is 100MHz? The curve in the data sheet is for a typical device, not worst case, and it shows you needing 5mV swing at the inpot to get a logic swing - 2.5V - at the outputs, a gain of about 500. The data sheet doesn't give upper and lower limits on maximim toggle frequency, but it does give worst case propagation delay ranges from 66% of nominal to 150% of nominal, which presumably scales with maximum toggle frequency. Your 100Mz sits on the worst case maximum toggle frequency that one might guess on this basis. I'd give myself a little more headroom. <snip> -- Bill Sloman, Nijmegen
From: Nial Stewart on 26 Jan 2010 10:42
Thanks again for the feedback Bill. > > Is this a problem if the input clock is 100MHz? > The curve in the data sheet is for a typical device, not worst case, > and it shows you needing 5mV swing at the inpot to get a logic swing - > 2.5V - at the outputs, a gain of about 500. > The data sheet doesn't give upper and lower limits on maximim toggle > frequency, but it does give worst case propagation delay ranges from > 66% of nominal to 150% of nominal, which presumably scales with > maximum toggle frequency. Your 100Mz sits on the worst case maximum > toggle frequency that one might guess on this basis. More details of the design.... Hmm. The 1mW into 50ohm input I'm told produces about 0.6V (not what I calculated but a real world measurement from the client). The maximum temp this will operate a is 70 Deg, with a 3.3V supply directly driving a clock buffer with max Cin of 6pF. The performance characteristics on page 5 (typical) would suggest that I'm no-where near even the 150MHz limit, even degrading this to 66% means I'm still OK. No? Nial. |