Termination of AC coupled 100MHz clok to generate low jitter 50MHz clock?
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From: Nial Stewart on 25 Jan 2010 06:40 I have a requirement to terminate an AC coupled 100MHz clock and produce an LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of jitter isn't specified). The input is specified as an "AC coupled signal of 1mW into 50 ohms". I don't have any experience with low jitter clock distribution so am unsure how to approach this. I currently have the clock terminated then ac coupled and biased into a LT1715 (150MHz comparator) feeding a single gate d type flip flop but am not confident this is the best approach. Once you've all stopped rolling around laughing, I'd appreciate any pointers to a better approach. Thanks in advance, Nial.
From: John Larkin on 25 Jan 2010 10:03 On Mon, 25 Jan 2010 11:40:28 -0000, "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >I have a requirement to terminate an AC coupled 100MHz clock and produce >an LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of jitter isn't >specified). > >The input is specified as an "AC coupled signal of 1mW into 50 ohms". > >I don't have any experience with low jitter clock distribution so am >unsure how to approach this. I currently have the clock terminated then >ac coupled and biased into a LT1715 (150MHz comparator) feeding a single gate >d type flip flop but am not confident this is the best approach. > >Once you've all stopped rolling around laughing, I'd appreciate any >pointers to a better approach. > > >Thanks in advance, > > >Nial. > That sounds reasonable. Expects low 10s of picoseconds RMS jitter, maybe below 10 if everything is perfect. Maybe worse if the signal is noisy. Adding a tuned circuit on the front end can help jitter performance a lot, by dumping ground loops, RF, any non-10-MHz stuff. If you design it to add a bit of voltage gain, even better. A faster comparator wouldn't hurt. LVDS line receivers make great:cheap fast comparators. John
From: Bill Sloman on 25 Jan 2010 11:41 On Jan 25, 12:40 pm, "Nial Stewart" <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote: > I have a requirement to terminate an AC coupled 100MHz clock and produce > an LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of jitter isn't > specified). > > The input is specified as an "AC coupled signal of 1mW into 50 ohms". > > I don't have any experience with low jitter clock distribution so am > unsure how to approach this. I currently have the clock terminated then > ac coupled and biased into a LT1715 (150MHz comparator) feeding a single gate > d type flip flop but am not confident this is the best approach. The LT1715 won't go faster than 150MHz http://www.datasheetcatalog.org/datasheet/lineartechnology/1715f.pdf as is shown on page 5 of the data sheet (above). A faster comparator might be a good idea. The Analog Devices AD96685 might be worth looking at, if you can live with ECL outputs. Their ADCMP567 seems to be quite a lot faster. http://www.analog.com/static/imported-files/data_sheets/ADCMP567.pdf but I've not used that device. John Larkin's point about a tuned circuit in the front end is a good one. I once used a half-wavelength of delay line between the inverting and non-inverting inputs of a comparator to get a little more voltage drive, but three feet of even minature coax could be a bit too bulky for comfort. -- Bill Sloman, Nijmegen
From: Nial Stewart on 25 Jan 2010 12:30 > The LT1715 won't go faster than 150MHz Bill, Is this a problem if the input clock is 100MHz? > The Analog Devices AD96685 might be worth looking at, if you can live > with ECL outputs. As usual my request wasn't fully spec'd. I'f prefer to power whatever I'm using just 3.3V, I can provide 5V if I _have_ to. > John Larkin's point about a tuned circuit in the front end is a good > one. I once used a half-wavelength of delay line between the inverting > and non-inverting inputs of a comparator to get a little more voltage > drive, but three feet of even minature coax could be a bit too bulky > for comfort. Space is fairly tight :-) Thanks, Nial.
From: John Larkin on 25 Jan 2010 14:28
On Mon, 25 Jan 2010 12:13:56 -0600, Tim Wescott <tim(a)seemywebsite.com> wrote: >On Mon, 25 Jan 2010 07:03:24 -0800, John Larkin wrote: > >> On Mon, 25 Jan 2010 11:40:28 -0000, "Nial Stewart" >> <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >> >>>I have a requirement to terminate an AC coupled 100MHz clock and produce >>>an LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of jitter >>>isn't specified). >>> >>>The input is specified as an "AC coupled signal of 1mW into 50 ohms". >>> >>>I don't have any experience with low jitter clock distribution so am >>>unsure how to approach this. I currently have the clock terminated then >>>ac coupled and biased into a LT1715 (150MHz comparator) feeding a single >>>gate d type flip flop but am not confident this is the best approach. >>> >>>Once you've all stopped rolling around laughing, I'd appreciate any >>>pointers to a better approach. >>> >>> >>>Thanks in advance, >>> >>> >>>Nial. >>> >>> >> That sounds reasonable. Expects low 10s of picoseconds RMS jitter, maybe >> below 10 if everything is perfect. Maybe worse if the signal is noisy. >> >> Adding a tuned circuit on the front end can help jitter performance a >> lot, by dumping ground loops, RF, any non-10-MHz stuff. If you design it >> to add a bit of voltage gain, even better. >> >> A faster comparator wouldn't hurt. LVDS line receivers make great:cheap >> fast comparators. >> >> John > >Note that if you're going into an impedance higher than 50 ohms that you >can get voltage gain from a resonant circuit. But if you design a >resonant circuit you either need some production guy to tune it or you >need to do some careful analysis to make sure that it works over >manufacturing variation and temperature. You'll definitely have a >tradeoff on the Q of the circuit -- higher Q means better noise >performance, but worse sensitivity to manufacturing gain. You can buy 2% surface-mount Rs and Cs these days, so something with a Q of three or so wouldn't be twitchey, and would jam a decent amount of swing into a comparator or LVDS receiver. Even at unity gain, a tuned circuit could help the jitter situation a lot. John |