Testbench
in [FPGA]
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From: maxascent on 30 Jun 2010 09:03 I am not sure if such a program exists, but I would like to be able to test a fairly large design by not having to write lots of testbenches. Idealy I would like a program were I could connect my DUT and give some constraints and then test vectors would be produced to test all cases within the constraints. Has anyone had any experience of such a program? Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: HT-Lab on 30 Jun 2010 09:29 "maxascent" <maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote in message news:ceydnR30ct0U3bbRnZ2dnUVZ_jWdnZ2d(a)giganews.com... >I am not sure if such a program exists, but I would like to be able to test > a fairly large design by not having to write lots of testbenches. Idealy I > would like a program were I could connect my DUT and give some constraints > and then test vectors would be produced to test all cases within the > constraints. Has anyone had any experience of such a program? No experience myself but have a look at inFact: http://www.mentor.com/products/fv/infact/ Hans www.ht-lab.com
From: d_s_klein on 30 Jun 2010 11:30 On Jun 30, 6:03 am, "maxascent" <maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I am not sure if such a program exists, but I would like to be able to test > a fairly large design by not having to write lots of testbenches. Idealy I > would like a program were I could connect my DUT and give some constraints > and then test vectors would be produced to test all cases within the > constraints. Has anyone had any experience of such a program? > > Thanks > > Jon > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com I auditioned Mentor's version of such a program. I assert that all programs of this type have the same failing: They are good at verifying that a design does what it does, they are not good at verifying that a design does what it is supposed to do. For a test, I created a module that intentionally got the Ethernet CRC wrong. The generated test bench passed the module with no comments at all. <RANT> There is a reason that good verification engineers charge good money for their talent. There is a reason that companies that delegate verification to junior engineers have such a hard time with verification. </RANT> RK
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