The Perfect Computer - 36 bits?
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From: jmfbahciv on 28 Mar 2007 07:52 In article <4609993a$0$18859$4c368faf(a)roadrunner.com>, Peter Flass <Peter_Flass(a)Yahoo.com> wrote: >Nick Maclaren wrote: >> >> It is a great pity that the new RISC systems (as distinct from previous >> inventions of the approach) concentrated entirely on making the hardware >> simple, often at the cost of making the software hell to get right. >> Which is one of the reasons that many aspects of modern software are >> so much worse than they were 25 years ago. >> > >I, as a programmer, shouldn't have to worry about ordering the >instructions so as not to lose cycles (pipeline slots, whatever.) >That's what hardware/microcode is for. Sure. But you are also a system owner and a system manager. Do the exercise and put each hat on and think from that point of view. You are also the hardware procurer who makes the sole decision of what you are going to purchase and plug in. /BAH
From: jmfbahciv on 28 Mar 2007 07:54 In article <460a483c$0$28137$4c368faf(a)roadrunner.com>, Peter Flass <Peter_Flass(a)Yahoo.com> wrote: >Quadibloc wrote: > > >> . >> Of course there isn't; RISC architectures almost by definition have >> clean ISAs. >> >> However, some CISC architectures do not. Specifically, the x86 >> architecture does not; since it is the *only* CISC architecture >> broadly available at this time, the lack which I refer to exists. > >I think all the IBM mainframe customers would disagree with this. We're >not dead yet;-) > It is worse than that. EVery PC system owner will be doing mainframe computing in the very near future. I wish I could some assess so they will wake up. /BAH
From: Jan Vorbrüggen on 28 Mar 2007 08:13 > I find this sad, as I would have liked to have a relatively elegant > and clean, but conventional, microprocessor available, such as the > 68020 architecture. ColdFire omits indexed memory access, which means > it omits too much. And for good reason: The indexed memory access is the 68020's most CISCy feature, and one variant is even worse than the VAX in this respect. Read up on John Mashey's classic post. Jan
From: jmfbahciv on 28 Mar 2007 08:05 In article <n8WdnY4v4J2jypfbRVnyhQA(a)bt.com>, Andrew Swallow <am.swallow(a)btopenworld.com> wrote: >jmfbahciv(a)aol.com wrote: >> In article <eubp25$628$1(a)gemini.csx.cam.ac.uk>, >> nmm1(a)cus.cam.ac.uk (Nick Maclaren) wrote: >>> In article <DZSdnaHeS49TzpTbnZ2dnUVZ8tXinZ2d(a)bt.com>, >>> Andrew Swallow <am.swallow(a)btopenworld.com> writes: >>> |> krw wrote: >>> |> > In article <fqWdnV-JLsRJ_ZXbRVnyiAA(a)bt.com>, >>> |> > am.swallow(a)btopenworld.com says... >>> |> >> Morten Reistad wrote: >>> |> >> >>> |> >> The only sensible use for the Alpha was to run microcode as a VAX. >>> |> >> When chip manufacturing technology allowed CISC CPUs on a single chip >>> |> >> the cost advantages of RISC were over. >>> |> > >>> |> > I think you'll find there are a few people who will disagree with >>> |> > you. >>> |> > >>> |> Probably but were they customers of DEC? >>> >>> Yes. >> >> What is it with this kid? I had so many woe-is-mes from customers >> about having to move to Micshits' stuff at that time. And I >> was not privy to the insides. These were people who I'd met on >> the newsgroups. > >The alternatives to the Alpha were VAX/VMS and PDP-11s not X86. No, those alternatives no longer existed. /BAH
From: Jan Vorbrüggen on 28 Mar 2007 08:14
> I, as a programmer, shouldn't have to worry about ordering the > instructions so as not to lose cycles (pipeline slots, whatever.) That's > what hardware/microcode is for. That's not an ISA question, that is a question of implementation. A modern out of order CPU and implement the same ISA - e.g., Alpha or x86 - without these constraints, while the in-order implementation requires them to gain performance. You get what you pay for in power, design complexity, transistors, and so on. Jan |