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From: Weng Tianxiang on 15 Feb 2010 18:59
Hi,
Recently I read Intel's a patent "Apparatus and a method for embedding
dynamic state machines in a static environment".

http://www.google.com/patents?hl=en&lr=&vid=USPAT5712826&id=yqIeAAAAEBAJ&oi=fnd&dq=5712826&printsec=abstract#v=onepage&q=&f=false

It direct uses the first level of latches in a normally 2 levels of
latches to do a dynamic state machine memory cell: storing information
of last half clock and driving through it without output gate to
control.

Directly driving through the first level of latches without switching
between two levels of latches.

Really unbelievable !

Weng



From: glen herrmannsfeldt on 15 Feb 2010 19:41
In comp.arch.fpga Weng Tianxiang <wtxwtx(a)gmail.com> wrote:

> Recently I read Intel's a patent "Apparatus and a method for embedding
> dynamic state machines in a static environment".
(snip)

Many intel processors historically used dynamic logic, though
without much explanation for what they actually did.

The 8080 and 8086 have minimum clock rates to satisfy the
dynamic logic in use.

> Directly driving through the first level of latches without switching
> between two levels of latches.

Would that also require a minimum clock rate? Or clocking
on both edges of a clock signal. The 8086, when clocked at
maximum frequency, requires a 33% duty cycle clock. At lower
frequencies that requirement isn't there.

-- glen
From: Eric Smith on 16 Feb 2010 01:11
On Feb 15, 4:41 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote:
> Many intel processors historically used dynamic logic, though
> without much explanation for what they actually did.

Someone at AMI published a book on PMOS logic design, which included
good material on the principles of four-phase and two-phase dynamic
PMOS logic. The same principles were generally applicable to NMOS.

> The 8080 and 8086 have minimum clock rates to satisfy the
> dynamic logic in use.

As did the original 186/188, 286, and 386. In particular the original
Intel 386 was dynamic even though it was CMOS; when AMD reverse-
engineered it they reimplemented the logic as fully static for their
386. The drawback was that the fully static design required a larger
die.
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